Fig. 1. Design and operation principle of our PM. (a) Schematic diagram of the PM’s structure, thermal distribution at a 6 V/500 ns voltage pulse, and optical mode profile at 2025 nm, respectively. (b) Operation principle of our PM. Simulated temperature variation of Sb2Se3 patch with applied single pulses of different voltages and durations for (c) crystallization and (d) amorphization.

Fig. 2. Device fabrication and switching performance of our PM. (a) Fabrication flowchart of the device. (b) Microscope image of an Sb2Se3 MRR PM. The inset shows an SEM image of the Sb2Se3 (the shaded region) on top of the PIN diode. (c) Normalized transmittance spectra of the PM after the phase switching between two states of Sb2Se3.

Fig. 3. The change in transmittance of the PM under multilevel states. (a) Amorphization (at 2024.59 nm) and (c) crystallization (at 2024.25 nm). The inset shows the enlarged error bar of two randomly chosen storage levels. Change in the transmittance of the PM with different voltages and pulse widths for (b) amorphization and (d) crystallization.

Fig. 4. Volatile modulation of an Sb2Se3 MRR. (a) Normalized transmittance spectra with different forward biases. (b) Dynamic response of the Sb2Se3 MRR.

Fig. 5. OCK based on the volatile-modulation-compatible PM. (a) Schematic architecture of a 4×4 OCK. The inset is the solidifying method of the output value of each basic unit in ONNs after on-chip training of OCK. (b) Schematic diagram of the on-chip training and writing operation of the OCK. The accuracy of predictions (c) after the simulated on-chip training of OCK and (d) after simulated writing into PMs.