Fig. 1. (Color online) The comparison of the circuit complexity and performance of diverse technologies in implementing the NAND/NOR logic gates circuit. Conventional CMOS technologies are unable to realize both NAND and NOR operations within a single circuit due to the fixed polarity of MOSFETs. Compared to the fixed polarity of CMOS transistors, a CMOS printing technique^[6] was used to integrate intrinsic silicon nanowires to construct transistors capable of being programmed as either n-type or p-type. Consequently, utilizing only four transistors allows for the fabrication of a reconfigurable NAND/NOR circuit. Moreover, the output anti-ambipolar characteristics of a reconfigurable dual-gated transistor^[8] based on 2D n-ReS₂/p-WSe₂ heterojunction are able to be controlled by the input voltages, therefore a single transistor can accomplish all the two-input logic operations including NAND and NOR, thereby significantly reducing the circuit complexity and enhancing the functionality of circuits.

Fig. 2. (Color online) An overview of the recent reconfigurable devices based on 2D materials for logic and analog applications^{[8, 25, 28−31]}.

Fig. 3. (Color online) Typical AAT devices. (a) Schematic of the fabrication process, (b) output characteristics, and (c) transfer characteristics of the gate-tunable SWCNT/MoS₂ heterojunction diode^[37]. (d) Schematic illustration of the self-aligned heterojunction transistor. (e) The rectification ratios of the BP/MoS₂ at different bottom-gate bias (V_BG) values. (f) I_D−V_TG characteristics of the heterojunction transistor at different V_BG. The inset in (f) shows the variation in transconductance^[28].

Fig. 4. (Color online) 2D reconfigurable AAT devices applied to reconfigurable logic circuits. Schematic illustrations of (a) the bottom-gated ReS₂/WSe₂ AAT and (b) the dual-gated ReS₂/WSe₂ AAT. (c) The transfer curves of the ReS₂-FET (blue) and WSe₂-FET (red) with V_d at 1.0 V. (d) The transfer characteristics of the dual-gated ReS₂/WSe₂ AAT. (e) The two-input logic operations are able to be demonstrated in a single dual-gated ReS₂/WSe₂ AAT^[8].

Fig. 5. (Color online) Nonvolatile reconfigurable multifunctional devices. (a) The schematic of the partial-floating-gate FET. The transfer characteristics of the partial-floating-gate FET acquired in (b) the reconfigurable memory mode and (c) the reconfigurable FET mode^[72]. (d) The schematic of the reconfigurable transistor based on ferroelectric CuInP₂S₆/MoTe₂ heterostructure. (e) Transfer curves of the CuInP₂S₆/MoTe₂ heterostructure transistor in symmetrically programming state (p−p and n−n doping). (f) Output curves of the transistor in asymmetrically programming state (p−n and n−p doping)^[73].

Fig. 6. (Color online) Nonvolatile devices used for logic-in-memory computing. (a) The schematic of the middle-floating-gate FET (MFGFET) based on WSe₂/h-BN/graphene vdWH. (b) Reconfigurable logic operations achieved in a single MFGFET. (c) The transfer curves of the MFGFET show a memory window. (d) The retention characteristics of the MFGFET^[71]. (e) Schematic illustration of the BP/ReS₂ heterostructure device. (f) The transfer curves of the BP-FET (blue) and the BP/ReS₂-FET (red), respectively. (g) The output characteristics of the ternary logic circuit based on a BP/ReS₂ heterojunction device. (h) The double swept voltage transfer characteristics of the ternary logic inverter circuit^[29].

Fig. 7. (Color online) 2D reconfigurable AAT devices applied to analog signal processing. (a) The three-dimensional schematic of the dual-gate WSe₂ transistor. (b) The transfer curves and the respective biasing configurations of the four modes (n-FET, p-FET, ambipolar, and anti-ambipolar) of the WSe₂ transistor. The frequency and phase operations achieved by the WSe₂ transistor in the condition of dark environment and (c) ambipolar or (d) anti-ambipolar modes^[36].

Fig. 8. (Color online) Spiking neuron based on 2D reconfigurable Gaussian heterojunction transistor (GHeT). (a) The fabrication process of the dual-gated GHeT based on SWCNTs/MoS₂ heterojunction. I_D−V_TG characteristics of the GHeT shows the control of (b) both sides of the anti-ambipolar response and of the peak position, (c) the height and (d) the peak position. (e) The diagram of the spiking neuron circuit that utilizing only one GHeT. (f) The experiment and simulation results of the GHeT spiking neuron exhibit spiking and resetting behaviors^[31].

Fig. 9. (Color online) AI hardware implementations based on 2D reconfigurable mixed-kernel heterojunction (MKH) transistors. (a) The schematic of the MKH transistor based on MoS₂/CNT heterojunction. (b) The mean, (c) amplitude, and (d) standard deviation of the Gaussian function in I_D−V_BG curves can be individually controlled by the V_TG. (e) The tunable sigmoid function shown in the I_D−V_TG curves. (f) I_D−V_TG curves of the MKH transistor exhibit both Gaussian and sigmoid characteristics with a tunable mixing ratio under different bias configuration of V_BG. (g) The circuit of the hardware implementation of a mixed-kernel support vector machine classification for arrhythmia detection, which only consists two MKH transistors^[99].

Fig. 10. (Color online) An FLS hardware based on the multi-gate van der Waals interfacial junction transistor (vdW-IJT). (a) Optical image of the lateral MoS₂/graphene junction. (b) Schematic of the multi-gate vdW-IJT with G1, G2, and a global top gate (TG). I_DS−V_G2 curves of the multi-gate vdW-IJT showing (c) π-shape and (d) Gaussian-like shape membership functions. (e) The image of a complete FLS hardware on a PCB (left) and detailed image of four membership function generators in a chip (right) ^[30].

Fig. 11. (Color online) AI hardware implementations based on 2D reconfigurable memristors. (a) The schematic of the threshold-switching memristor based on the vertical MoS₂/graphene vdWH. (b) The circuit of the artificial neuron based on only one threshold-switching memristor. The output spikes of the artificial neuron circuit that exhibiting (c) integration period and (d) refractory period. (e) The stochastic distribution characteristics of V₁ and V₂ by repeating the switch of HRS/LRS^[116]. (f) The schematic of the three-terminal stochastic memristor based on SnO_x/MoS₂ heterostructure. (g) The P_ss,t<2s− (V_TE − V_TE0) curves of the stochastic memristor show exponential-class sigmoidal distributions. (h) The relationship of the effective "temperature" (T_eff) and V_g. (i) The schematic of the Boltzmann machine circuit where each stochastic neuron consists only one stochastic memristor and a simple peripheral circuit^[25].