In the past few decades, the semiconductor technology has undergone remarkable development and transformation since the silicon began to be widely studied as a semiconductor material in the mid-20th century, which results in the great success in communication, Internet and other high technology industries. On the one hand, since the first transistor was invented in 1948, the size of transistors has been dramatically decreased due to the improvement of manufacturing processes, materials and the revolution of field-effect transistor (FET) structures from planar transistor to Fin-FET and gate-all-around FET^[1]. On the other hand, the integration density of integrated circuits has developed rapidly following the Moore's law, which enables the fabrication of large-scale integration and even ultra-large-scale integration, thus accelerating the development of computers, smartphones, microprocessors and other electronic products.

However, several limitations have appeared in recent years as the semiconductor technology moving towards submicron scale. Firstly, Moore's law is approaching the physical limit when the size of semiconductor devices decreases under 10 nm, which also causes the challenges in manufacturing process, short-channel effect and reliability of traditional transistors^{[2, 3]}, whereas the emerging advanced materials and devices bring the issues of compatibility, design complexity and manufacturing cost. In addition, the increase of leakage current results in the issue of trade-off between power consumption, noise margin and performance requirements^[4].

To avoid the limitations caused by the size of semiconductor devices, realizing reconfigurable and multiple functions in the same circuit has been explored as another way to improve integration density and performance of integrated circuits. So far, complementary metal−oxide−semiconductor (CMOS) technologies have already been used to fabricate scalable multifunctional circuits and flexible electronics^{[5, 6]}, which were designed to complete complex logic or analog functions in a single circuit. However, the field-effect characteristics in the traditional metal−oxide−semiconductor FET (MOSFET) are limited and relatively fixed because the electrical properties and carrier transport in the conventional semiconductor materials are often hardly to control. As a result, reconfigurable circuits based on traditional MOSFETs require additional circuits that consist of many electronic components to achieve reconfigurability^[7], which lead to complicating the system design and fabrication process as well as substantial power consumption.

Instead, reconfigurable devices that can realize reconfigurable characteristics and multiple functions at device level provides a method to overcome the challenges above. As an emerging semiconductor device, reconfigurable device can achieve real-time and tunable reconfigurability of its properties according to practical demands, such as polarity-switching and control over transfer characteristics. Therefore, compared to traditional CMOS technologies that use unipolar transistors, using reconfigurable devices to achieve the same circuit functions can significantly reduce the usage of devices and other components as well as the power consumption and footprint. For instance, Fig. 1 depicts a comparison of the circuit complexity and performance of CMOS technology, CMOS printing technique^[6] and reconfigurable device^[8] in implementing the NAND/NOR logic gates circuit. As the improvement of the reconfigurable functionality of devices, there is a significant enhancement of circuit performance and reduction of circuit complexity.

Currently, two-dimensional (2D) materials are the main candidates for reconfigurable device fabrication. Since the monolayer graphene was first fabricated in 2004, 2D materials have attracted significant attention all over the world^[9]. Different 2D materials also have been widely studied in the fields of electronics and optoelectronics due to their unique properties including varying bandgaps and tunable properties, such as graphene, transition metal dichalcogenide (TMDs), hexagonal boron nitride (h-BN), overmetallic oxide and black phosphorus (BP)^[10−12]. Firstly, layered 2D materials have an ultrathin structure without any dangling bond, which simplifies the fabrication process of van der Waals heterostructures (vdWHs) and other devices based on 2D materials, as well as enhances the immunity of these devices to the short-channel effects and the thin-body channel of conventional semiconductors^[13]. The ultrathin nature of 2D materials also enables effective transport control and injection tunability of both types of carriers, which are the key prerequisites for realizing reconfigurability in the device level. The lack of dangling bond also significantly suppresses the surface recombination and dark current which are very unfavorable to photodetectors^[14]. Additionally, the diverse and tunable electrical properties of 2D materials not only make them ideal for various electronical devices, but also allow them to cover a wide range of electromagnetic spectrum responses for photodetection applications^[15]. Furthermore, 2D materials allow the modulation of structural defects, such as grain boundaries and point defects, which can tune the intrinsic properties of 2D materials and thus enables the formation/dissolution process of conductive channels that are vital in the switching of high or low resistance state. Expect electrical properties, 2D materials also exhibit outstanding optoelectrical characteristics such as quantum confinement and strong light−matter interactions^[16]. Because of these outstanding characteristics, 2D materials hold strong potential in constructing reconfigurable devices and photodetectors. A comparison between 2D reconfigurable device and traditional CMOS transistor is listed in Table 1.

Currently, "top down" and "bottom up" are the main methods for the growth of 2D materials. Traditional "top down" methods like mechanical exfoliation prepare large-area 2D material films by reducing the dimensions of bulk materials, therefore the films can inherit the crystal structures of the bulk materials^[17]. Although it is a cheap and efficient method, this approach needs further improvements in crystal quality and large-scale production^[18]. "Bottom up" methods are usually used to grow large-scale 2D materials by assembling atoms or molecules, commonly used techniques include chemical vapor deposition, pulsed laser deposition and molecular beam epitaxy^{[17, 18]}. There are two main routes for the growth of 2D materials on substrates: nucleation and growth of a single nucleus and the seamless coalescence of aligned 2D material grains^[18]. For instance, through the nucleation and growth of a single nucleus on substrate, wafer-scale graphene monolayers have been successfully synthesized. Wafer-scale h-BN monolayer^[19] and centimeter scale MoS₂ film^[20] have also been synthesized on tailored substrates through the seamless coalescence of aligned 2D grains on the substrates. These advanced growth methods promote the application of 2D materials in reconfigurable devices.

The unique properties of 2D materials bring them significant advantages in logic and analog applications. For logic applications based on 2D reconfigurable devices, a high on/off current ratio and a rapid switching speed are the most crucial requirements^[21]. In order to fulfill these requirements, the relevant 2D materials need to exhibit high carrier mobility and low defect density to improve the switching speed and the stability of the carrier transport, as well as a high carrier concentration to increase the current at the on state. Because of the suitable bandgap and high mobility under short channel condition, TMDs hold great potential for logic applications^[22]. For example, MoS₂ films are commonly employed as n-type semiconductor and exhibit relatively high mobility and on/off current ratio^[23]. Other TMDs with appropriate bandgap such as ReSe₂ and WSe₂ also exhibit much higher on/off ratio, a reconfigurable transistor based on WSe₂ has been reported with an on/off ratio exceeding 10⁷ for both n-types and p-types^[24].

As for analog applications, high carrier mobility and low defect density are still essential for achieving high performance. However, in certain 2D materials like MoS₂, defects can be modulated to simulate the function of synapses, which is the working principle of some memristors^[25]. Another important requirement for analog applications is the precise control over the carrier transport in the devices, which requires the electronical properties in 2D materials can be precisely controlled. Fortunately, the electronic properties and band gap of 2D materials such as BP and TMDs can be controlled by the layers number, heterostructure, external electric field and other methods^[26]. For example, the band gap of BP can be adjusted from 0.3 to 2.0 eV by the number of BP layers^[21]. In addition, although graphene are not ideal for logic applications due to its low on/off ratio resulting from its zero band gap, utilizing graphene as the contact material offers many significant advantages, including the reduction of the interface states at the graphene-semiconductor interface and the enhanced tunability of electronical properties through the applied input voltages^[27].

This review aims to provide an overview of the recent reconfigurable devices based on 2D materials as well as their logic and analog applications that have been reported in recent years. The structure of this review is outlined in Fig. 2. We will present these devices in terms of both logic and analog applications. As for the devices that are used in logic applications, we will introduce two categories of devices that can generate tunable anti-ambipolar characteristics and demonstrate nonvolatile operations at the device-level, we will also analyze the working principle, output characteristics and related logic applications, including logic operations and logic-in-memory computing. On the other hand, we will summarize the anti-ambipolar transistors (AATs), reconfigurable transistors and reconfigurable memristors that are applied to analog applications, such as analog signal processing circuits and the emerging artificial intelligence (AI) hardware implementations. Finally, we will discuss the challenges and outlook of the 2D reconfigurable devices.

By controlling the gate voltage of a traditional MOSFET, we can easily change the working regions of a MOSFET, thereby obtaining the switching of the on/off states in the output currents. Therefore, MOSFETs can be used to implement simple logic circuits such as electronic switches and logic gates. However, when it comes to more complicated logic functions, CMOS technologies have to use a large number of MOSFETs, which causes large parasitic resistance and high delay of the circuit. The increase of static leakage current also can't be neglected.

Compared to MOSFETs, reconfigurable devices have more flexible transport properties and scalability due to the advantages of 2D materials, which make them well suited for complicated logic circuits. In this Section, we will review two commonly used reconfigurable devices in logic circuits, AATs and nonvolatile memories, as well as describing their respective functions and applications.

Utilizing the weak van der Waals interaction between 2D materials, vdWHs can be built through the stacking of different layered 2D materials, which avoids the issues of lattice mismatch and interface defects between different materials, but also preserves the unique properties of each layer^[32−34]. Therefore, semiconductor devices based on 2D vdWHs exhibit numerous unique and promising properties in the fields of electronics and photonics^[35]. Among them, anti-ambipolar characteristic is one of the most attractive properties, which refers to the Λ-shaped transfer curve of the heterojunctions, and can be used to achieve advanced logic functions^{[29, 36]} and neuromorphic computation.

The first AAT device with gate-tunability was reported in 2013^[37]. In this study, a gate-tunable p−n heterojunction diode was created by semiconducting single-walled carbon nanotubes (SWCNTs) and single-layer MoS₂, which was used as p-type and n-type semiconductor layer, respectively. Fig. 3(a) shows the fabrication process and structure of the SWCNT/MoS₂ heterojunction diode. By applying a bias voltage V_G to the gate electrode of the diode, the electrostatic doping of the semiconductor layers can be controlled by the applied V_G due to the atomically thin nature of 2D layered materials. Therefore, the charge transport behavior of this p−n heterojunction shows a wide tunability from nearly insulating to highly rectifying, as shown in Fig. 3(b). Moreover, within a certain range of V_G, the transfer characteristics of the device shows an anti-ambipolar behavior (Fig. 3(c)) that can be qualitatively explained as originating from the channel consisting of p-type and n-type semiconductors in series, which also has a high on/off current ratios up to 10⁴.

In the next few years, the AAT devices based on 2D vdWHs have witnessed rapid development, various combinations of 2D materials were used to build AATs such as p-WSe₂/n-MoS₂ vdWH transistor^{[38, 39]}, p-WSe₂/n-WS₂ vdWH transistor^[40], p-BP/n-MoS₂ heterojunction^[41], SnS₂/WSe₂ heterojunction-based AAT^[42]. However, there was still a lack of a method to simultaneously achieve the fabrication of short channel and large footprint devices, and the relative alignment between different layers in 2D vdWHs was restricted by the diffraction resolution of transfer and alignment techniques^[28].

In 2018, a self-aligned, semi-vertical and source-gated architecture^[28] was reported to overcome these shortcomings and fabricate a p-BP/n-MoS₂ heterojunction transistor with a short channel length of less than 150 nm, Fig. 3(d) shows the schematic illustration of the self-aligned heterojunction transistor. The asymmetry architecture in the transistor allows the source-gated configuration where the bottom electrode (drain) is biased while the overlapping electrode (source) is grounded, which results in an extra depletion region near the drain contact and therefore improves current saturation and reduces short channel effect. Fig. 3(e) shows the rectification ratio of the BP/MoS₂ at different bottom-gate bias (V_BG) values.

Moreover, in the dual-gated architecture, due to the screen effect of the MoS₂ layer on the bottom gate, the BP layer is controlled only by the top gate. Similarly, the overlapped MoS₂ layer underneath BP is controlled only by the bottom gate because of the screening of top gate, while the nonoverlapped MoS₂ layer is controlled by both gates. This architecture provides controlled and improved electrostatic doping as well as the gate-tunability of the heterojunction, thus enables the control of all characteristics of the anti-ambipolar response. As shown in Fig. 3(f), the anti-ambipolar response of the heterojunction transistor can be tuned by V_BG, which is also reproduced by finite-element simulation. These characteristics give this hereoterjunction transistor a unique advantage in signal processing applications and scalable frequency amplifiers and mixers.

Negative differential resistance (NDR) devices that have a high peak-to-valley ratio (PVR) have been regarded as the key components of logic circuits. Compared with the NDR devices that need to be operated in a low temperature environment, AATs can exhibit anti-ambipolar characteristic that is similar to the NDR behavior and achieve high PVRs at room temperature^[43]. Therefore, AATs hold a great promise for various kinds of logic circuits, such as reconfigurable logic gate operations^{[8, 44]} and multi-valued logic (MVL) circuits^{[29, 37, 38, 45, 46]}.

Single-electron transistors^[47] and CMOS technology have been used to realize multiple logic gate operations, but they need to face the issues of cryogenic temperature environment and extensive use of transistors, respectively. In contrast, there were numerous AAT devices reported to achieve reconfigurable logic gate operations in a single device at room temperature. In 2022, A dual-gate organic AAT was fabricated to achieve reconfigurable five two-input logic operations^[44].

In 2023, a dual-gated AAT based on 2D ReS₂/WSe₂ heterojunction was fabricated to achieve all the reconfigurable two-input logic operations in a single transistor^[8], where WSe₂ and ReS₂ were used as p-type and n-type semiconductors in the heterojunction, respectively. Figs. 4(a) and 4(b) show the schematic illustration of a bottom-gated AAT and a dual-gated AAT where the top electrode covers the channel area, respectively. Fig. 4(c) shows the transfer curve of a ReS₂-FET (blue) that exhibits n-type characteristics and a WSe₂-FET (red) that exhibits ambipolar characteristics. Moreover, compared with the threshold voltage of n-type ReS₂-FET, WSe₂-FET's threshold voltage of the p-type condition was much higher, which enables the dual-gated AAT to demonstrate anti-ambipolar characteristics when these two FETs are both in the on state. Fig. 4(d) shows the Λ-shaped anti-ambipolar transfer curves of the ReS₂/WSe₂ AAT with different top-gate voltage (V_tg) while the drain bias (V_d) is fixed at −3 V. It should be noted that the peak voltage is clearly dependent on V_tg while the peak width remains almost the same (~1.1 V) due to the WSe₂-FET's ambipolar characteristics. These unique properties are important for the implementation of reconfigurable logic operations. Therefore, by optimizing the input voltages, all the two-input logic operations can be demonstrated in a single dual-gated AAT, including AND, OR, XOR, NAND, NOR, and XNOR (Fig. 4(e)), which is significant for simplifying circuits design and improving integration density.

MVL circuits can benefit the integration density by increasing the number of logic states^[48], which are significant for next-generation high performance digital electronics^[49]. As one of the most significant applications of the MVL circuits, the first ternary inverter based on 2D vdWH was reported in 2016 using a MoS₂/WSe₂ heterojunction^[38]. This ternary inverter can be qualitatively equivalent to a WSe₂-FET in series with a MoS₂/WSe₂ Hetero-FET, where the MoS₂/WSe₂ Hetero-FET exhibits anti-ambipolar characteristics. After that, many studies have reported ternary inverters based on different AATs, such as organic AATs^{[45, 50]}, BP/ReS₂ heterojunction transistors^[46], BP/MoS₂ heterojunction transistors^[41], photosensitive graphene p−n junction AATs^[51] and MoTe₂/MoS₂ heterojunction transistors with photoinduced doping^[52]. In 2020, a 2D vdWH based on BP and ReS₂^[29] was created to demonstrate nonvolatile ternary logic operations for the first time. In addition to ternary inverters, other MVL applications also have been realized by using AATs, including quaternary inverters^{[53, 54]}, ternary latches and static random-access memory^[55] based on AATs with M-shaped transfer curves.

To overcome the bottleneck of the conventional von Neumann computing architecture, where the computing and storage of increasing data are separated and thus causing the issues of significant latency and energy consumption^[4], nonvolatile devices for in-memory computing that can realize data processing and storage in the same device have attracted intensive attention^{[29, 56]}. By shortening the distance of data transmission, nonvolatile devices are expected to achieve high efficient data computing and processing with lower energy consumption^[57]. Because of the dangling-bond-free surface, atomical thickness, and diversity of energy band structures^[58−60], 2D materials are promising candidates for the building of nonvolatile reconfigurable devices, including multifunctional devices^[61−64], nonvolatile memory^[65−69] and logic-in-memory computing devices^{[29, 70, 71]}.

In addition to realizing specific reconfigurable and tunable function in a single device, another approach to improve the integration intensity is to realize nonvolatile multifunction in the same device, thus allowing these devices to achieve diverse functions or change working modes according to different external conditions. For example, the polarity of a traditional CMOS transistor can't be changed after fabrication due to the physical doping of the drain/source regions, but the polarity of 2D reconfigurable transistors can be switched during run-time due to the electrostatic doping nature of 2D materials^[73] or the photo-induced doping^[74]. Moreover, the design of nonvolatile reconfiguration allows lower energy consumption and higher reliability of these devices. Previous 2D nonvolatile reconfigurable devices were mostly built on floating-gate structures using MoS₂^[75], WSe₂^[76], MoS₂/MoTe₂^[77] as channel materials, in which the floating gate controls the charge storage layer.

However, in the devices above, different operations were always controlled by the same terminal, resulting in the issues of reliability and versatility. In 2022, a 2D graphene/hBN/WSe₂ heterostructure transistor was fabricated to perform as reconfigurable nonvolatile memory and polarity-switchable FET with a partial floating-gate serving as the charge-trapping layer^[72]. Fig. 5(a) shows the schematic of the partial-floating-gate FET (PFGFET), where the partial floating-gate (CG) and top field (TG) gate provide efficient electronic control of the contact region and WSe₂ channel, respectively. Fig. 5(b) shows the transfer curves of the PFGFET set in reconfigurable memory mode, which are obtained by sweeping the CG voltage (V_CG) forward and backward between −8 and 8 V with V_D = 0.1 V and V_TG = ±0.2 V. The PFGFET can exhibit both n-type (V_TG = 2 V) memory and p-type (V_TG = −2 V) memory with a reduced V_CG and an erase/program ratio of 10⁸ for both modes. This device can also be operated in polarity-switchable FET mode, when TG and CG act as input and trigger terminal, respectively. The transport characteristics in Fig. 5(c) are obtained by sweeping V_TG between −2 and 2 V after applying a V_CG pulse of ±8 V to the PFGFET, the curve in the left part exhibit p-type behavior (V_CG-pulse = −8 V) while the right one shows n-type behavior (V_CG-pulse = 8 V). Moreover, both transport behaviors of n-type and p-type mode show a small hysteresis and high on/off ratio about 10⁸. These outstanding characteristics make the PFGFET suitable for many logic-in-memory applications including linear/nonlinear logic gates and half-adder, which are attributed to the partial floating gate that significantly improves the carrier injection in contact region, where a sufficiently negative V_CG-pulse can simultaneously induce a small hole Schottky barrier and a large electron Schottky barrier at the interface of metal/semiconductor, then resulting in a high on/off ratio.

The stable spontaneous polarization nature of ferroelectric materials enables ferroelectric FETs (FeFETs) based on the stack of ferroelectric/semiconductor to achieve different functions with nonvolatile properties, including reconfigurable memory^[78−80], optoelectronic photodetectors^{[81, 82]} and electronic/optoelectronic synapses^{[83, 84]}. Zhao et al. built a nonvolatile reconfigurable transistor based on 2D ferroelectric CuInP₂S₆/MoTe₂ heterostructures in 2021^[73], and the structure of the device is shown in Fig. 5(d). The electrodes above the CIPS and below the dielectric layer serve as the program gates (PG) and back gate (BG), respectively. The nonvolatile properties are attributed to the ferroelectric dipoles in CIPS that contribute to the doping of electron/hole in MoTe₂, which can be maintained after cutting off power supply. To be specific, the polarization condition in the CIPS maintained almost the same in 1 h during the retention test. Moreover, the contacts of drain and source are sandwiched between the channel and BG, resulting in the screen of the field from BG, thus providing better individual electrostatic control of this device. When the device is operated in the nonvolatile reconfigurable transistor mode, the doping conditions of the drain and source contacts are programmed individually. Fig. 5(e) shows the transfer curves of the reconfigurable transistor with V_DS = 1 V in symmetrically programming state (p−p and n−n doping), where both contacts act as the reservoirs of the carriers, thus exhibiting p-type or n-type unipolar behavior. In contrast, Fig. 5(f) shows the output curves of the transistor with V_BG = 0 V when the contacts are programmed asymmetrically (p−n and n−p doping), exhibiting rectifying behaviors in both conditions. What's more, this device can also be used to exhibit a series of tunable photo response, where p−p doping and n−n doping states generate positive and negative photocurrent, respectively, whereas the asymmetrical states can exhibit strong photovoltaic effect. These nonvolatile reconfigurable and optoelectronic characteristics of the device have a great potential in future computing and sensing system implementations.

There are also other approaches used to achieve 2D nonvolatile reconfigurable devices. In 2023, using a photoinduced trapping mechanism that can drive photoexcited carriers into the interface of h-BN/SiO₂ and Si substrate, a reconfigurable transistor based on h-BN/ReSe₂/h-BN heterostructure was reported with nonvolatile tunable polarity^[85], which can be used to create logic circuits and emulate synaptic functions. An effective-gate-voltage-programmed graded-doping strategy^[7] was used to fabricate a single-gate MoTe₂ transistor in the same year, which can be programmed to different operation modes including polarity-switchable diodes, in-memory logic gates and electronic synapses. A three-gate reconfigurable FET was also proposed as synaptic devices, which allowed the NOR/XNOR operations in the binary neural network^[86].

Logic-in-memory computing, which refers to the integration of logic operations in nonvolatile memory units, has a great advantage in saving transistors and energy consumption for nonvolatile logic applications. So far, various device structures based on 2D materials have been used to realize logic-in-memory computing, such as vdWHs^{[29, 72, 87]}, floating-gate FETs^{[71, 75, 88, 89]} and FeFETs^{[70, 80]}.

In 2023, a middle-floating-gate FET (MFGFET) was fabricated by Sheng et al. using a 2D WSe₂/h-BN/graphene vdWH^[71]. Fig. 6(a) depicts the schematic of the MFGFET based on WSe₂/h-BN/graphene heterostructure, where WSe₂, h-BN and multilayer graphene serves as the channel material, tunneling layer and floating gate, respectively. In particular, the graphene floating gate is aligned with the middle of the WSe₂ channel in the middle-floating-gate architecture, which allows the central part of the channel to be controlled by the floating gate. Therefore, by controlling the voltages of the middle floating gate (V_MFG), control gate (V_CG), drain and source (V_DS), the polarity and current level of the MFGFET can be adjusted between n-type and ambipolar behavior. Taking advantages of these properties, reconfigurable logic operations of AND (V_DS = 0.5 V) and XNOR (V_DS = 3 V) can be achieved in a single MFGFET, where V_CG and V_MFG act as input signals IN1 and IN2, current I_DS acts as output signal I_OUT (Fig. 6(b)). Moreover, since the charge-trapping function of the middle floating gate, the reconfigurable logic functions can be integrated into the nonvolatile memory with the trapped charges playing the role of stored logic operand. Fig. 6(c) shows the nonvolatile behavior of the MFGFET, where exists a memory window in the transfer curves with the V_CG sweeping forth and back, and a high erase/program current ratio up to 10⁴ at V_CG = 0 V. By programming/erasing the device with a V_CG-pulse and then reading the current states, the retention characteristics of the MFGFET are shown in Fig. 6(d), where all the current states retain well within 800 s, thus showing a reliable data storage capacity.

In 2019, using a graphene floating gate surrounded by dielectric layers to store charges, a dual-gate floating-gate FET^[88] with a MoS₂ channel was fabricated to achieve photo-switching logic operations (OR/AND) and in situ memory in a single device. Except serving as the input signals in the logic operation mode, the voltages of dual gate can also be used to carry out write operations, which can store the logic states in the floating gate. Similar functions can also be realized by a 2D dual-gate transistor based on the stack of Al₂O₃/HfO₂/Al₂O₃^[90], which serves as the dielectric layer as well as trapping or releasing charges.

Utilizing the electrical hysteresis effect of ferroelectrics, FeFETs can be used to realize nonvolatile memory by substituting ferroelectrics for oxides as the dielectric layer^[91]. In 2022, a dual-gate FeFET based on MoS₂ and MoTe₂^[70] was explored to form nonvolatile logic gates (including AND, OR, XNOR) for both digital and analog in-memory computing. In 2020, more advanced logic functions with memory ability including flip-flop and d-type latch were carried out by unipolar memristors for the first time based on MoS₂/graphene/HfSe_2−xO_x vdWHs^[87].

Except traditional binary logic operations, MVL circuits can also be realized by nonvolatile devices. In 2020, based on 2D BP/ReS₂ vdWHs, an anti-ambipolar device was demonstrated for nonvolatile ternary logic operations^[29]. Fig. 6(e) shows the schematic of the BP/ReS₂ heterojunction device, which is built on a HfO₂-coverd silicon substrate. Fig. 6(f) shows the transfer curves of the BP-FET and the BP/ReS₂-FET with the drain voltage fixed at 1 V. It's worth noting that the transfer curve of the BP/ReS₂-FET exists a negative transconductance region, which derives from the band-to-band n-type hole tunneling caused by the drain bias pulling down the energy band of BP. Therefore, ternary logic circuits can be achieved by a BP-FET and a BP/ReS₂-FET in series. Fig. 6(g) shows the output characteristics of the ternary logic circuit based on a BP/ReS₂ heterojunction device with V_dd increasing from 0.1 to 2 V, and the inset shows the schematic diagram of the circuit. This circuit can demonstrate three distinct logic states including "1", "0" and an additional "1/2". Moreover, due to the natural oxidation of the BP layer, there is an ultrathin phosphorus oxide (PO_x) layer on the surface, which serves as the band−band tunneling layer and the charge trapping layer at the same time, thus resulting in an obvious hysteresis and memory states under the condition of double voltage sweep (Fig. 6(h)). Utilizing these characteristics, this device can be used to demonstrate nonvolatile ternary logic operations with low energy consumption and small footprint.

Apart from the logic circuits that compute discrete signals, analog circuits that process continuous signals are also essential in practical applications. However, with the increase of the scale and complexity of circuits, analog circuits based on traditional CMOS technology are facing the issues of noise and the trade-off between performance and power consumption.

With special designs, reconfigurable devices based on 2D materials are able to generate multiple transfer characteristics with precise tunability, which makes them more flexible in different analog applications. In this Section, we will review the analog signal processing applications of AATs. Furthermore, we will discuss the 2D reconfigurable transistors and memristors that have been used to implement various AI hardware.

As mentioned in Section 2.1, the Λ-shaped transfer curves of AATs enable both positive and negative transconductances to be exhibited in a single device. Moreover, the architecture of dual-gate provides controllable electrostatic doping and the gate-tunability of the AAT, thus enables the control of the anti-ambipolar response^[28]. These characteristics bring AATs unique advantages in analog signal processing applications^[32], such as phase shift keying, frequency multipliers and frequency mixing.

Previous frequency multipliers usually consisted of nonlinear electronic components. In 2020, a frequency doubling circuit was demonstrated based on AAT devices, where the device is built from the 2D MoTe₂/MoS₂ heterojunction^[92]. This frequency doubler consisting of only one device can operate well within 3 kHz, which significantly reduce the number of transistors that needed to achieve frequency multipliers compared to conventional CMOS methods. Furthermore, a graphene-bridge based AAT device was demonstrated to achieve a frequency tripler in 2023^[93], which used laterally series-connected ambipolar WSe₂/graphene/MoS₂ as the channel of the AAT device that shows N-shaped transfer curves.

Combining the advantages of the ambipolar and anti-ambipolar characteristics can enhance the reconfigurability and tunability for frequency modulation applications. In 2021, a WSe₂ transistor that can exhibit both ambipolar and anti-ambipolar transfer curves was reported for the first time^[36], which was built on an ambipolar WSe₂ channel with dual-electrostatic control and source/drain Schottky barriers. Fig. 7(a) shows the three-dimensional schematic of the WSe₂ transistor. A dual-gate structure, G_B and G_C, was used to control the transport of the transistor, which separately decide the polarity of the Schottky barrier and the channel, thus controlling the transfer characteristics. Fig. 7(b) shows the transistor's transfer curves of the four modes (n-FET, p-FET, ambipolar and anti-ambipolar) and the respective biasing configurations, with the mobility of 1.8 and 1.7 cm²/(V·s) for holes and electrons, respectively. In the condition of dark environment and ambipolar/anti-ambipolar modes, the transistor can achieve frequency and phase operations in the output current waveforms, including double frequency, in-phase and out-of-phase, as shown in Figs. 7(c) and 7(d). It is worthy noted that there was a phase shift of ±90^° between the output waveforms of the ambipolar and anti-ambipolar modes. These characteristics of the WSe₂ transistor benefit the analog modulation/encoding schemes and 2/3-bit data transmission as well as reduce fabrication complexity of the AATs.

In addition to frequency multipliers, AAT devices also have been used to implement phase shift keying (PSK) and frequency shift keying (FSK) circuits, which are widely used in the technologies of wireless data transmission, microwave radio and telecommunications. CMOS technologies^[94] and 2D ambipolar transistors^[95] have already been used to design PSK and FSK circuits. In 2015, an AAT device based on a SWCNT/a-IGZO heterojunction^[96] was reported to enable PSK operations that are dependent on the out sine, as well as the FSK operations utilizing the combination of one heterojunction device in series with a load resistor. Using the same WSe₂ transistor and similar circuit configuration^[36] can also demonstrate the PSK function. In particular, under the illumination of 532 nm, the transfer curves of the transistor in the anti-ambipolar mode exhibit a significant left shift compared to the dark characteristics.

Inspired by the behaviors of the human nervous systems, AI technologies have developed rapidly in recent years and played an important role in neuromorphic computing, which can effectively improve the efficiency and reliability of data processing. Moreover, the hardware implementations of AI algorithms enable the neuromorphic computing at hardware-level, thus avoiding the issues of latency and stability caused by the limitations of network bandwidth and massive data. Because of its unique energy band structures and rich electronic properties, 2D materials are strong candidates for devices that can realize reconfigurable analog functions for AI algorithms. Up to now, various 2D reconfigurable transistors have been reported for the hardware implementations of AI algorithms.

Kernel functions, including linear, Gaussian, polynomial and sigmoid functions, are widely used to map input vectors from the origin space into a high-dimensional characteristic space in AI algorithms such as neural networks, support vector machine (SVM) and logistic regression. As one of the most commonly used kernel functions, Gaussian functions are widely used in many AI applications, such as artificial neural networks based on Gaussian synapses^{[97, 98]}, spiking neurons for spiking neural networks (SNNs)^[31] and SVMs for classification tasks^[99]. Although silicon-based CMOS technologies have already been used to build digital and analogue hardware for the generation of Gaussian functions, but they both consist massive transistors and other elements, resulting in large footprint and high power consumption, which makes them impossible to achieve real-time and off-grid applications of AI technologies. Additionally, the additional circuits of CMOS hardware require a large number of transistors and complicated structures, which limits the integration density and scalable implementations of the AI computing systems.

Utilizing the weak electrostatic screening properties^[100], AAT devices based on 2D materials can generate gate-tunable and reconfigurable Gaussian response under suitable biases, which is of great importance of the hardware-level neuromorphic computing. So 2D AAT devices have been exploited to generate tunable Gaussian responses in a single device, thus simplifying the hardware implementations of AI applications and the additional circuits.

For example, SNN, which uses discrete spikes and the incorporation of time, can dramatically improve the energy efficiency of neuromorphic computing by mimicking the behaviors of nervous system more graphically^[101]. Except CMOS technologies, several approaches have been explored to realize neuromorphic functionality for spiking neurons at device level, such as NbO_x based metal−insulator transition (MIT) devices^[102], ultrathin 2D TiO_x nanosheets^[103], diffusive memristors^[104] and FeFETs^[105], but these approaches still face many challenges including limited output swing and incomplete synaptic functions. In 2020, a Gaussian heterojunction transistor (GHeT) was fabricated for spiking neurons implementations based on 2D SWCNTs/MoS₂ heterojunction^[31]. Fig. 8(a) shows the fabrication process of the dual-gated GHeT structure, where the monolayer MoS₂ and solution-processed CNT exhibit n-type and ambipolar behavior in this structure, respectively. Moreover, due to the dual-gate, self-aligned structure and electrostatic screening effect, the CNTs can be fully controlled by top gate (TG) and partially controlled by the bottom gate (BG), whereas the monolayer MoS₂ can be fully modulated by the BG and partially modulated by the TG. Therefore, the diversity of current combinations modulated by TG and BG enable the reconfigurability and gate-tunability of the Gaussian response in a single device, Figs. 8(b)−8(d) show the Gaussian curves of the GHeT with controlled anti-ambipolar response, height and peak position under different biasing configuration.

Taking advantages of the tunable Gaussian response of the GHeT, this device can be used to build a circuit-level spiking neuron. The diagram of the full spiking neuron circuit is shown in Fig. 8(e), which consists one GHeT, two n-FETs (T1 and T2) and other elements including capacitors, resistors and voltage sources. The GHeT spiking neuron is able to exhibit spiking and resetting behaviors in both experiments and simulations by emulating the behavior of Na⁺ conductance, which is shown in Fig. 8(f). The GHeT device significantly simplifies the structure of the spiking neuron circuits, which enables the scalable SNN applications with lower energy consumption.

In addition to Gaussian functions, other kernel functions and mixed-kernel functions are also important in many AI algorithms, especially in SVMs that carry out classification and identification tasks. In 2023, a reconfigurable mixed-kernel heterojunction (MKH) transistor^[99] was reported to generate reconfigurable Gaussian/sigmoid mixed-kernel function that can be controlled by the dual gates. Fig. 9(a) show the dual-gated and semi-vertical architecture of the MKH transistor based on 2D MoS₂/CNT heterojunction, which allows the dual gates controlling both the overlap and non-overlap regions of MoS₂ and CNT. Utilizing the weak electrostatic screening of the overlap region, the MKH transistor can generate Gaussian functions through sweeping the voltage of the back gate (V_BG), and the amplitude, mean and standard deviation of the Gaussian function can be individually controlled by the biasing configuration of the top gate (V_TG), which are shown respectively in Figs. 9(b)−9(d). Moreover, as shown in Fig. 9(e), the MKH transistor can also yield tunable sigmoid function by sweeping V_TG with a fixed V_BG, which was observed for the first time in anti-ambipolar devices. Therefore, tuning the bias condition of V_BG enables the I_D−V_TG curves of the MKH transistor exhibit both Gaussian and sigmoid characteristics with a tunable mixing ratio, as shown in Fig. 9(f). Additionally, the MKH transistors were used to demonstrate the hardware implementation of a mixed-kernel SVM classification for arrhythmia detection from ECG data, where the full circuit (Fig. 9(g)) consists only two MKH transistors. The mixed-kernel function generated by MKH transistors can significantly improve the personalized classification accuracy to about 90 %. It's worth noting that compared to traditional CMOS implementations that require at least 100 transistors, this MKH approach has outstanding advantages in reducing transistor usage, footprints and energy consumption, which is more significant in wearable applications and scalable implementations such as n × n kernel matrix.

Utilizing the charge effect at the interface of different 2D materials, by modulating the configurations of bias voltages, 2D reconfigurable devices can generate output characteristics with varying shapes and parameters to meet the requirements of different AI algorithms. In 2024, a multi-gate van der Waals interfacial junction transistor (vdW-IJT) based on a MoS₂/graphene heterostructure was reported to generate tunable Gaussian-like and π-shaped membership functions (MFs)^[30]. As shown in Fig. 10(a), in the lateral junction of heavy n-doped (n⁺) MoS₂ layer and p-doped graphene ribbon, the overlapping graphene region exhibits light n-type (n⁻) doping due to the transporting of electron from MoS₂ to graphene. Therefore, the vdW-IJT has a lateral structure of n⁺/n⁻/n⁺ homojunction in the MoS₂ channel, thus resulting in precise and effective control of doping level and carrier transport properties through the charge transfer effect at the interface. By applying different gate bias voltage configurations to the multi-gate vdW-IJT shown in Fig. 10(b), a single multi-gate vdW-IJT is able to generate π-shape and Gaussian-like shape I_DS−V_G2 curves. When V_G1 < 1 V, I_DS is mainly determined by V_G2 as electrons can pass through G1. With the increase of V_G2, I_DS changes from being blocked to gradually increasing until saturation, and finally decreasing due to the recombination current becomes larger, thus resulting in the π-shape curves that can be modulated by V_G1 as shown in Fig. 10(c). Similarly, if V_G1 > 1 V, I_DS begins to increase from a certain voltage because V_G2 must be large enough to prevent the electrons from leaking through G1, and I_DS begins to decrease due to the recombination current in G2, therefore the Gaussian-like shape curves was demonstrated in Fig. 10(d). Moreover, detailed parameters of these curves can be adjusted by V_TG and V_DS, which makes the vdW-IJT more suitable for applications.

Using the tunable Gaussian-like and π-shaped MFs, by being integrated with peripheral CMOS circuits, the multi-gate vdW-IJT can be used to create a fuzzy logic system (FLS) hardware, which can be operated as a fuzzy proportional–integral–derivative (PID) controller, as shown in Fig. 10(e). FLSs essentially represents a nonlinear mapping between the input space and the output space. The MFs generated by vdW-IJT not only effectively enhance the nonlinear mapping ability, but also make the PID controller more flexible and adaptable when interacting with humans, which resulting in a remarkable improvement in the performance of a fuzzy neural network (FNN) in image segmentation tasks. Moreover, other significant advantages of this vdW-IJT method include scalability and power cost.

In addition to specific functions, stochastic characteristics are also essential for many non-von-Neumann computing architectures including Boltzmann machines (BM). So far, memristors have been widely used to generate parameters and distributions with stochastic characteristics due to their various stochastic properties, which dependent on the random motions of the atoms and ions. In 2018, a horizontal MoS₂ memristor that is able to control the resistive state and thus showing memristive behaviors was reported, which is realized by the migration of defects in the MoS₂ film^[106]. In addition to the defect migration^[107−109], phase transitions in 2D materials can also result in memristive effects^{[110, 111]}. Therefore, a large number of neuromorphic computing implementations have been explored based on different kinds of memristors, including artificial neural networks^{[104, 110, 112, 113]}, annealing systems^[114], and true random number generators^[115].

For example, a threshold-switching memristor (TSM) was constructed based on the vertical MoS₂/graphene vdWH in 2019^[116]. Fig. 11(a) shows the schematic of the vertical MoS₂/graphene TSM, where the vertical structure allows the large-scale fabrication and high-density integration of the device^[117]. This TSM device abruptly converts from high resistance state (HRS) to low resistance state (LRS) when the voltage of graphene electrode (V_Gr) increases to V₁. Similarly, the device abruptly reverts to HRS when V_Gr decreases below V₂. These nonvolatile switching characteristics of the threshold voltage are originating from the migration of oxygen ions in the MoS₂ layer, where the multiple grain boundaries (GBs) in the polycrystalline structure of the MoS₂ offer the migration channels.

Utilizing the switching characteristics, this TSM device was used to demonstrate an artificial neuron to reproduce the integration and refractory response of biological neurons. Fig. 11(b) shows the circuit diagram of the artificial neuron, which is consisted of one TSM device along with resistors and a capacitor (Co). Figs. 11(c) and 11(d) show the output spikes of the artificial neuron circuits that exhibiting integration and refractory period, respectively, where the input pulses have an amplitude of 8 V and a frequency of 5 kHz. These behaviors are generated by the threshold voltage switching of the TSM and the trapping/releasing of charge in Co. In addition, the frequency of spikes can be controlled by the amplitude of input pulses, which also mimics the characteristics of biological neurons. Furthermore, by repeating the switch of HRS/LRS for 40 times, we can observe the stochastic distribution characteristics of V₁ and V₂ as shown in Fig. 11(e), which are attributed to the stochastic nature from the motions of oxygen ions in MoS₂. These unique properties make the TSM device promising in neuromorphic sensors, hardware security and other real time computing applications.

However, the probability distributions of these memristors are not stable and cannot be precisely modulated, which limits their applications in the hardware implement of neural networks. To overcome these challenges, a three-terminal SnO_x/MoS₂ heterostructure memristor was reported to generate stochastic distributions with dynamically tunable parameters in 2021^[25]. The architecture of the hetero-memristor is shown in Fig. 11(f), the amorphous SnO_x layer, which serves as the filament-switching layer, is sandwiched between the top electrode (TE) and the MoS₂ layer. Utilizing the stochastic characteristics in the filament-formation process that originating from the ionic random motion, this hetero-memristor can be used to demonstrate tunable statistical distributions from the set process, where the memristor is switched from high-resistance state to low-resistance due to the formation of the filament. By applying a V_TE to a high-resistance memristor, the probability that the memristor is successfully set within 2 s (P_ss,t<2s) shows exponential-class sigmoidal distributions in Fig. 11(g), where V_TE0 refers to the V_TE point of 50% probability. Moreover, the P_ss,t<2s curves also show that the gate bias (V_g) can modulate the 0−1 transition of the sigmoidal distributions, which is attributed to V_g tuning the electrical properties of MoS₂, thus controlling the potential distribution between SnO_x and MoS₂. Furthermore, the P_ss,t<2s distribution can be approximated to a Fermi−Dirac like distribution (Pss,t2s≈11+exp(−VTE−VTE0Teff)), where the effective "temperature" (T_eff) can be dynamically controlled by V_g (Fig. 11(h)).

Taking advantages of this hetero-memristor, a BM using simulated annealing based on reconfigurable stochastic neurons was demonstrated to solve a MAX-SAT problem. Each stochastic neuron consists only one memristor and a simple peripheral circuit, as shown in Fig. 11(i). More importantly, the tunable nature of the device allows the T_eff of the BM be dynamically tuned by V_g, thus enabling different "cooling" strategies of the BM, which avoids premature convergence and improves the accuracy of the BM, as well as reducing the usage of electronic elements and energy consumption.

Although a large number of studies have demonstrated the extraordinary advantages of 2D reconfigurable devices, there still lies several challenges in the growth of 2D materials and the fabrication process of these emerging devices.

First of all, in order to achieve the practical applications of 2D materials, having high-quality single crystalline wafer-scale 2D materials is of paramount importance. At present, since mechanical exfoliation method is not suitable for wafer-scale production, the best way to achieve wafer-scale 2D materials is bottom-up growing on the substrate. However, our current understanding of the growth and nucleation mechanisms of 2D materials under various conditions remains incomplete. This lack of comprehensive knowledge hinders the development of synthesis methods for wafer-scale 2D materials and brings significant challenges in controlling thickness, defects and lattice mismatch^[118], while the method for manufacturing multilayer structures still awaits development. What's more, current seamless coalescence technology imposes strict requirements on the substrate processing^[119].

In the fabrication process of 2D vdWHs, the lack in the methods of transfer and stacking 2D materials layers limits the large-scale integration of 2D reconfigurable devices^[120], for example, wrinkles, defects, or cracks may occur on 2D material films while transferring devices. As a result, current 2D reconfigurable devices usually are faced with the issues of low device yield and high variability^[121]. Moreover, influenced by the compatibility with silicon-based technology, leakage current and limited supply voltage, the performance of these devices also needs further improvement. To take the 2D reconfigurable devices into practical applications, the design complexity of the devices and corresponding circuits is another challenge apart from the limitations that have been mentioned above.

In this article, we began with introducing the limitations of traditional semiconductor technologies and reconfigurable circuits in improving integration density. Consequently, we introduced the outstanding characteristics of 2D materials and reconfigurable devices based on 2D materials that can realize reconfigurable functions at device level. To provide a review on the recent progress of emerging reconfigurable devices based on 2D materials and their related logic or analog applications, we introduced these devices from two perspectives: their functions at device level and their logic or analog application at circuit level. One notable feature of 2D reconfigurable devices is their ability to generate tunable anti-ambipolar characteristics, which are originated from the weak van der Waals interaction and effective control of transport conditions in 2D materials. We introduced the mechanism of typical AAT devices and summarized their applications in logic operations. Another significant function of 2D reconfigurable devices is demonstrating nonvolatile operations, which are achieved by the special design of floating gates and ferroelectric materials. We explained the working principles of several nonvolatile devices and introduced the devices that have nonvolatile multifunction and are used to realize logic-in-memory computing. As for the analog applications of AATs, we reviewed the analog signal frequency modulation circuits based on AATs. Furthermore, we introduced diverse AI hardware implementations that utilize reconfigurable transistors and memristors, highlighting the unique advantages of reconfigurable devices in the hardware applications. Finally, we discussed the challenges of current 2D reconfigurable devices and summarized the full article.