Fig. 1. Schematic diagram of DC. The selection of a logic operation is performed using reconfigurable illumination without any modification to the DOEs.

Fig. 2. Forward and backward processes of DC. The reconfigurable illumination, the DOEs, and the scaling factor are optimized through the training process.

Fig. 3. Optimization results. (a) Binary amplitude patterns on a DMD for the reconfigurable illumination and (b) phase distributions on the DOEs. Scale bar is 1 mm.

Fig. 4. Examples of the DC process with the optimized illumination and the DOEs shown in Fig. 3. (a) Test input pair of random patterns and its corresponding (b) ground truths of the 16 operations, with the operation index l noted below each, and (c) their operation outputs, with the RMSE noted below each. (d) Test input pair of characteristic patterns and its corresponding (e) ground truths of the 16 operations, with the operation index l noted below each, and (f) their operation outputs, with the RMSE noted below each. Scale bars in (a) and (d) are 1 mm, indicating the physical scale after the upsampling process.

Fig. 5. Computational errors associated with the varying number of DOEs.

Fig. 6. Computational errors associated with the varying number of DOEs for single logic operations.

Fig. 7. Error trends during the training process.

Fig. 8. Computational errors associated with the varying number of DOEs for single logic operations. (a) 1≤l≤4, (b) 5≤l≤8, (c) 9≤l≤12, and (d) 13≤l≤16.

Fig. 9. Computational errors associated with the varying physical volume of DC.

Fig. 10. Computational errors under different positions of the input layer.

Fig. 11. Relationship between computational errors and energy efficiencies when varying the scaling factor.

Fig. 12. Relationship between computational errors and energy efficiencies with the varying buffer width (BW [pixels]).

Fig. 13. Relationships between computational errors and alignment errors along the x axis on the layers (a) between the illumination and the one before the input (1≤k≤5), and (b) between the input and the end (6≤k≤11); and those along the z axis on the layers (c) between the illumination and the one before the input (1≤k≤5), and (d) between the input and the end (6≤k≤11).

Fig. 14. Candidates for the experimental setups of DC using (a) transmissive phase modulation with DOEs and (b) reflective phase modulation with SLMs.