Optical computing is a longstanding and captivating topic in the fields of optics and photonics. It is considered a potential post-Moore computing technology1 that offers distinct advantages, including high bandwidth, rapid processing speed, low power consumption, and parallelism.2^,3 Around the 1980s, optical computing was actively explored, with developments in technologies, such as optical vector matrix multipliers4^–7 and optical associative memories.8^–10 Among these, shadow casting (SC) emerged as a prominent optical computing technology of that era.11^–14 SC facilitated single instruction, multiple data (SIMD) for logical operations through optical and spatially parallel computing. The SC scheme relied on shadowgrams, which optically generated a single output image through massively parallel logic operations from two binary input images. The versatility of SIMD logic operations was attained by altering the illumination pattern of the shadowgrams. Another key aspect involved the computational encoding and decoding of input and output images, respectively, designed to balance light intensities between the zeros and ones in the binary images. This computational process was an obstacle in achieving end-to-end optical computing. Despite the anticipated benefits in speed and energy efficiency, these optical computing technologies in the 1980s stagnated due to limitations in hardware (fabrication) and software (design) for optical components at that time. As a result, they lagged behind the major progress made in electronic computing.

Over the past few decades, significant advancements in microfabrication, mathematical optimization, and computational power have dramatically transformed the field of optical computing from what it was in the 1980s. Several pioneering optical computing techniques have been studied, including waveguide-based photonic circuits and diffractive neural networks (DNNs). Waveguide-based photonic circuits, which integrate waveguide interferometers, have high compatibility with currently existing electronic computers and circuits. They have led to a wide range of applications, such as vector-matrix operations,15^–17 logical operations,18^–24 and integrated reconfigurable circuits.25^–27

DNNs consist of cascaded diffractive optical elements (DOEs), which emulate neural network connections as light waves pass through the DOEs. This configuration utilizes the spatial parallelism of light and realizes fast and energy-efficient computation. A wide range of attractive applications based on DNNs has been proposed, including image classification,28^–33 image processing,34^–37 linear transformations,38^–40 and logic operations.41^–47

Currently, the demand for computation in SIMD logic operations has intensified, particularly due to advancements in cutting-edge technologies such as image processing, machine learning, and blockchain.48^–50 Traditional computation with central processing units is often inadequate to meet the computational needs of these fields. Consequently, graphics processing units,51 tensor processing units,52 field-programmable gate arrays (FPGAs),53^,54 and application-specific integrated circuits55^,56 are employed as SIMD-specific devices. The trend towards high-speed, energy-efficient, and massively parallel computing aligns well with the advantages of optical computation. As a result, there has been a rapid increase in efforts to develop practical optical computing methods for SIMD logic operations. Optical SIMD logic operations have been achieved using waveguide photonic circuits.26^,27 However, a drawback of this approach is its limited scalability, which arises from the need for precise yet large-scale fabrication.

The use of DNNs holds potential as a solution to this issue, owing to the parallelism inherent in free-space propagation. For instance, several types of DNN-based logic operations have been proposed to overcome this drawback,41^–47 but these previous methods typically involve only one or a few types of logic operations on a small number of bits, and the realization of SIMD logic operations using DNNs remains unachieved. Moreover, these methods still require computational encoding and decoding of the input and output, respectively, posing a significant challenge for end-to-end optical computing, similar to the SC scheme.

In this study, considering the background mentioned above, we present a method termed diffraction casting (DC) for conducting all 16 optical SIMD logic operations on more than one hundred bits by incorporating the SC scheme and DNNs. DC revives SC through the use of DNNs. Therefore, DC shares the motivation of SC but exhibits several differences and advantages over SC. Unlike SC, which is based on geometrical optics, DC is grounded in wave optics. As a result, DC incorporates wave phenomena such as diffraction and interference through the use of DOE cascades in DNNs and is anticipated to offer greater integration capability compared to SC. Another advantage of DC is its elimination of the need for computational encoding and decoding of the input and output, respectively, which have been inherent bottlenecks in the SC scheme and previous DNN-based logic operations referred to above. This is enabled by introducing a buffer area around the input pair. In the rest of the paper, we will elaborate on the architectural design of DC, including the forward model, the optimization process, and provide numerical demonstrations.

DC is designed for 16 types of SIMD logic operations, processing two input binary images to produce one output binary image. Figure 1 depicts the conceptual architecture of DC. DC consists of a reconfigurable illumination, DOEs, and an input layer. The reconfigurable illumination enables switching between logical operations and casts light on the DOE cascade forming a DNN. In this paper, we focus on the reconfigurable illumination with binary amplitude modulation implemented using a digital micromirror device (DMD) illuminated with coherent light from a laser, and on DOEs with phase modulation, assuming the use of commercially available optical components.

We place the two input images side by side on the input layer within the DOE cascade to achieve a simple optical setup. The output of the logic operation appears as an intensity distribution at the end of the cascade and is captured with an image sensor. The final result is binarized by assuming a one-bit image sensor or a computational process. The reconfigurable illumination and DOEs are specifically trained to perform the 16 SIMD logic operations on any two binary images, as detailed in the subsequent subsection. Once the training process is completed, DC enables massively parallel optical logic operations on arbitrary binary inputs just by selecting the illumination patterns, without necessitating any modifications to the DOEs.

Figure 2 illustrates the forward and backward processes of DC. We consider a total of L types of SIMD logic operations on N parallel bits. These operations are conducted by an optical cascade composed of K layers, including one illumination layer, one input layer, and K−2 DOE layers, with the layer index denoted as k∈{1,2,…,K}. The first layer of the optical cascade is the binary reconfigurable illumination rl∈{0,1}Px×Py, where l∈{1,2,⋯,L} is the index of the logic operations. An input pair f∈{0,1}Nx×2Ny, composed of side-by-side binary images, is located on the input layer, denoted as the Kin’th layer in the cascade.

Here, Nx and Ny represent the pixel counts of the individual images within the input pair along the x and y directions, respectively, where Nx×Ny=N. The phase distributions for each DOE layer are denoted by ϕk∈RPx×Py, and Px and Py indicate the pixel counts of the DOEs along the x and y axes, respectively. The result of the logic operations is observed with the image sensor located downstream of the K’th layer in the optical cascade.

We now describe the forward process of DC. The complex amplitude modulation vk∈CPx×Py, induced by the reconfigurable illumination, input pair, and the phase-only DOEs at the k’th layer in the cascade, is expressed as vk={rlfork=1,I[f]+tfork=Kin,exp(jϕk)otherwise,(1)where j denotes the imaginary unit. Here, I is an operator transforming the input pair into an amplitude image on the input layer, composed of the following two steps. The first step is upsampling along the x and y directions with factors of sx∈N and sy∈N, respectively. The second step is zero padding to enlarge the upsampled input pair to the DOE size (Px×Py pixels). t∈{0,1}Px×Py expresses a buffer surrounding the upsampled input pair, as illustrated in Fig. 2 and is defined as follows: t(ux,uy)={0for{ux,uy}∈(Px−sxNx2,Px+sxNx2]×(Py−2syNy2,Py+2syNy2],1otherwise,(2)where ux∈N and uy∈N are indices along the x and y directions. This buffer is employed to compensate for light intensities transmitted or blocked on the input pair and enables the removal of computational encoding and decoding of the input and output, processes that are indispensably employed in previous optical logic operation methods, including the SC scheme.

The propagation process passing through the k’th layer in the cascade is written as wk+1=Dk[vkwk],(3)where wk∈CPx×Py is a complex amplitude field just before the k’th layer. Dk is a diffraction operator representing the propagation from the k’th layer to the (k+1)’th layer, calculated based on the angular spectrum method.57 The initial field w1 is specified as an all-ones matrix, indicating a uniform field at the start.

The output intensity field of the optical cascade is observed with the image sensor as follows: h=aO[|wK+1|2],(4)g=B[h].(5)Here, h∈RPx×Py represents the intermediate field, obtained through an operator O that first crops the central sxNx×syNy pixels from the output intensity field and then downsamples it to the original input image size of Nx×Ny. This process includes scaling the intensity by a factor of a∈R>0, which corresponds to either amplifying or attenuating the signal. g∈RNx×Ny is the final result of the logic operation, with the binarization operator B defined as B[b]={0forb<0.5,1forb≥0.5,(6)where b∈R is an arbitrary variable. The binarization process, which converts analog signals to Boolean ones, is implemented using either a one-bit image sensor or through computational means. The variation of the threshold in the binarization is not crucial to the performance of DC. This is because the scaling factor a in Eq. (4) is optimized for the threshold through the gradient descent process, as described in the next section, and thus neutralizes the impact of the threshold.

To realize optical logic operations in parallel, the illumination rl, the DOEs ϕk, and the scaling factor a are optimized based on gradient descent in this study. First, we describe the optimization process by assuming a single logic operation (L=1) and a single input pair for simplicity, where the illumination is defined as rL=1. Then, we extend the optimization process to arbitrary numbers of logic operations and input pairs.

We define a cost function e for a single logic operation and a single input pair based on the mean squared error (MSE) as follows: e=1N∑∀|e|2,(7)where ∑∀ represents the summation of all the elements of a tensor on its right side. Here, the error e is defined by e=h−g^,(8)which represents the difference between the intermediate field h and the ground truth of the operation result g^. This is to avoid the intermediate field’s signals around the threshold values in B, ensuring a robust binarization process.

To optimize rL=1 and ϕk based on gradient descent, the partial derivatives of e with respect to these variables are expressed by employing the chain rule as follows: ∂e∂rL=1=∂v1∂rL=1·∂e∂v1,(9)∂e∂ϕk=∂vk∂ϕk·∂e∂vk.(10)

The right sides of these partial derivatives include the partial derivative of e with respect to vk, calculated as ∂e∂vk=4aNwk*Dk−1[vk+1*Dk+1−1[⋯[vK*DK−1[wK+1O−1[e]]]⋯]],(11)where Dk−1 and O−1 are operators representing the inverse processes of Dk and O, respectively, and the superscript * denotes the complex conjugate.

The partial derivatives with respect to each optimized variable are finally written as follows. The partial derivative with respect to rL=1 is described as ∂e∂rL=1=Re[∂e∂v1],(12)where Re[·] denotes the real part of a complex amplitude. The partial derivative with respect to ϕk is described as ∂e∂ϕk=Re[−jvk*∂e∂vk].(13)The partial derivative with respect to a is described as ∂e∂a=2aN∑∀he.(14)

Next, we extend the optimization process from a single logic operation and a single input pair as described above, to L logic operations and M input pairs. In this scenario, the cost function E based on the MSE is expressed as E=1LM∑l,mel,m,(15)where el,m denotes the cost associated with the l’th logic operation and the m’th input pair, derived from Eq. (7). The partial derivatives of E with respect to rl, ϕk, and a are presented as summations of the partial derivatives of el,m with respect to these variables, derived from Eqs. (12)–(14), respectively, ∂E∂rl=∑m∂el,m∂rl,(16)∂E∂ϕk=∑l,m∂el,m∂ϕk,(17)∂E∂a=∑l,m∂el,m∂a.(18)

The variables rl, ϕk, and a are updated with the partial derivatives in Eqs. (16)–(18) based on the Adam optimizer.58 The updating processes for the DOEs ϕk and the scaling factor a are described as follows: ϕk←ϕk−Adam[∂E∂ϕk],(19)a←a−Adam[∂E∂a],(20)where Adam[·] represents an operator to calculate the updating step in the Adam optimizer with the derivatives. To simplify the physical realization of the illumination rl, we assume its binary implementations, such as DMDs, by introducing stochastic perturbations into the gradient descent process.59 The first step in the update process for the variables is as follows: rl˜←C[rl˜−Adam[∂E∂rl]],(21)where r˜l is an intermediate variable for the backward process in the optimization of rl. Here, C is an operator for clipping the range of values as follows: C[b]={0forb<0,1forb>1,botherwise.(22)Subsequently, rl in the forward process is updated as follows: rl=B[r˜l+q],(23)where q∈RPx×Py is a uniform distribution between ±0.5, introduced to avoid local minima in the binary optimization. After the optimization process, rl is finalized as follows: rl=B[r˜l].(24)

We numerically demonstrated DC with all 16 logic operations (L=16) for the Boolean input pair fleft and fright, as shown in Table 1. In this numerical demonstration, the wavelength of the coherent light for the reconfigurable illumination λ was defined as 0.532μm. The optical cascade comprised eleven layers (K=11), incorporating nine DOEs, with the input layer positioned as the sixth layer (Kin=6). The intervals between the layers were equally set to 3×104λ(≈1.60×104μm). For the illumination pattern rl, the DOEs ϕk, and the input layer, the pixel pitch was 16λ(≈8.51μm). This pixel pitch was chosen by considering commercially available spatial light modulators (SLMs), including DMDs, as well as the microfabrication technique used for configuring DOEs,60 and the simplicity of using an integer product.44^,45 The pixel count was 160 (=Px) along the x axis and 288 (=Py) along the y axis, respectively. For the input pair fm, the pixel count of the individual image in the pair was 16 (=Nx) along the x axis and 16 (=Ny) along the y axis, where the parallel bits N became 256, and the upsampling factors sx and sy were both 8. The width of the region with ones on the buffer t, as defined in Eq. (2), was set to 16 pixels. To prevent the circulant effect on the diffraction calculation, the complex amplitude fields were zero-padded with a width of 64 pixels during the layer-by-layer propagation processes.

For the optimization process, the input pairs were generated with values initially selected from uniform random distributions between 0 and 1 and were then binarized using randomly selected thresholds, also between 0 and 1. The numbers of input pairs for training and testing were 80,000 and 256, respectively, without any duplication. The batch size M was set to 16 for training. The number of iterations was 5000. The learning rates for the Adam optimizer, as used in Eqs. (19)–(21), for rl, ϕk, and a were set to 3×10−2, 1×10−2, and 3×10−3, respectively. These variables were initially set to uniform random distributions for rl and ϕk, and 10 for a. The final performance of DC with L logic operations was evaluated by the root mean squared errors (RMSEs) between the final result gl,m and the ground truth g^l,m for M test input pairs, as shown in Fig. 2 and described as follows: RMSE=1LMN∑l,m∑∀|gl,m−g^l,m|2.(25)

The optimization results for the illumination rl and the DOEs ϕk are presented in Figs. 3(a) and 3(b), respectively. The scaling factor a was optimized to 23.8. In the numerical demonstration shown in Fig. 4, DC was performed using two test input pairs with 256 parallel bits. The first pair, shown in Fig. 4(a), was composed of random patterns. The second pair, shown in Fig. 4(d), was composed of characteristic patterns. Ground truths of their 16 SIMD logic operations are displayed in Figs. 4(b) and 4(e), respectively. The operation outputs are shown in Figs. 4(c) and 4(f), respectively, where all operations were successful, and their RMSEs were zero. Furthermore, the RMSEs for 256 test input pairs of random patterns were also found to be zero. These outcomes underscore the promising potential of DC. More detailed discussions are provided in the next section and the appendix.

We conducted numerical analyses of the performance of DC under various optical conditions. Throughout this analysis, the experimental conditions were consistent with those described in Sec. 3, except where otherwise noted. Further analyses are provided in Appendix A.

The computational performance of DC, with the number of DOEs set to K−2, was evaluated using the RMSEs, as illustrated in Fig. 5. In this evaluation, the number of input parallel bits N was set to 4, 16, 64, 128, and 256. Correspondingly, the upsampling factors along the x and y axes were adjusted to (64, 64), (32, 32), (16, 16), (8, 16), and (8, 8) [=(sx,sy)], respectively, aiming to maintain consistent pixel counts of 128 (=sxNx,syNy) on the input layer after upsampling. The layer index of the input layer Kin was set to ⌊(K−2)/2⌋+2. When the number of DOEs was zero, only the illumination pattern was optimized.

As illustrated in Fig. 5, the calculation error decreased with an increase in the number of DOEs. Additionally, the necessary number of DOEs for achieving error-free calculation increased with the number of input parallel bits N, but at a rate less than proportional to N. This rate of increase was smaller than predicted in previous works,32^,38 indicating an advantage of DC in terms of scalability and integration capability through the use of spatially parallelized optical processes for logic operations.

The DOEs implemented 16 logic operations in a multiplexed manner in DC, as shown in Table 1. We confirmed the computational errors under different numbers of DOEs, denoted as K−2, when the optical cascade was designed for single logic operations. The layer index of the input layer, Kin, was set to ⌊(K−2)/2⌋+2. In Fig. 6, computational errors for AND, OR, NAND, and NOR operations, selected from the 16 operations, are shown. Results for all 16 logic operations are provided in Fig. 8. In most of these results, error-free or nearly error-free calculations for single logic operations were achieved when the number of DOEs was greater than 6. On the other hand, as shown in Fig. 5, the necessary number of DOEs for multiplexing 16 logic operations was 9, which is significantly less than 6×16, for error-free calculations. Furthermore, the computational errors for some logic operations, such as XNOR and NOR, were reduced by multiplexing all the logic operations, which may help prevent falling into local minima in the optimization process. These results verified the advantage of multiplexing logic operations, in terms of both architecture configuration and training process, as well as the integration capability of DC.

We revived SC as DC by employing DNNs to achieve scalable and flexible optical SIMD operations. The optical cascade of DC consisted of reconfigurable illumination, DOEs, and an input layer. The illumination patterns and DOEs were designed to perform 16 logic operations on any binary input image pair, and the output intensity of the optical cascade was binarized to produce the final results. In this study, we achieved 16 switchable logic operations on 256 bits, which is an outstanding achievement compared with previous studies.41^–47 In contrast to these methods, where the optical diffraction processes from each spatial region of logic operations and bits must be separately designed, our method allows both interference between spatial regions of bits and interference between logic operations, enabling these regions to be densely located based on end-to-end designs of the illumination patterns and DOEs. This advantage has enabled high scalability and integration capability with all-optical operation, eliminating the need for computational encoding and decoding, all of which were numerically demonstrated.

An issue with DC for practical applications is its low energy efficiency. This may be addressed by adopting illumination with phase modulation and optimizing physical conditions, including the layer interval, buffer, and image sensor. We are planning the physical implementation of DC based on the setups shown in Sec. 7. Owing to its flexible and reconfigurable architecture offered by a learning-based approach, DC can be extended to a versatile range of inputs and operations beyond SIMD logic operations, such as image processing, including image filtering, and advanced reconfigurable optical computing methods like optical FPGAs. Furthermore, incorporating multiplexing in various optical quantities, such as time,61^,62 wavelength,63 polarization,39^,64 and orbital angular momentum,42 would enhance the computational capacity in DC. Thus, our study on DC offers a novel design architecture for optical computers and optical accelerators and paves the way for a next-generation optical computing paradigm.

This appendix provides detailed analyses of DC. Throughout this appendix, the experimental conditions are consistent with those described in Sec. 3, except where otherwise noted.

Figure 7 illustrates the trends of the cost function based on the MSE without the binarization process in Eq. (15) and the computational error based on the RMSE in Eq. (25) during the training process. At the end of the training process, the cost function converged to nearly zero but not exactly zero. On the other hand, the computational error converged to exactly zero around the final iteration step. This indicates that the binarization process rectified the optical outputs and eliminated their small errors.

The code for the numerical demonstrations in this study was implemented with MATLAB 2022a (MathWorks) and was executed on a computer with an AMD EPYC 7763 64-core processor at a clock rate of 2.45 GHz and an NVIDIA A100 SXM4 with 80 GB of memory. The computational time for the entire training process was ∼7 h.

In Sec. 4.2, the computational errors of DC designed for single-logic operations of AND, OR, NAND, and NOR were selectively presented. The errors for all 16 logic operations are shown in Fig. 8. In most logic operations, error-free or nearly error-free calculations were achieved when the number of DOEs was greater than ∼6. On the other hand, multiplexing all 16 logic operations achieved error-free calculation when the number of DOEs was 9, as shown in Fig. 5, which was much smaller than 6×16 and supported the advantage of multiplexing the logic operations.

The physical volume of the optical cascade in Sec. 3.2 was calculated as 3.89×1012λ3(≈5.86×1011μm3), where the pixel pitch on the DOEs was 16λ and the intervals between the layers in the optical cascade were 3×104λ, respectively. We investigated the computational error with respect to the reduction of the physical volume by scaling down both the pixel pitch and the interval with the same magnification ratio, varying the pixel pitch from 1/8λ to 16λ by powers of two. The result is shown in Fig. 9. In this case, the minimal physical volume without computational error was 5.94×107λ3(≈8.94×106μm3), where the pixel pitch was λ(=0.532μm), and the interval was 1.17×102λ(≈6.23×10μm). This result indicated that the minimal physical volume of DC is constrained by the diffraction limit.

The computational error was calculated by varying the position of the input layer Kin from 2 to 11 in the optical cascade with 11 layers, as depicted in Fig. 10. This result shows the importance of the DOEs downstream from the input layer in reducing computational error. It suggests that there is an advantage in positioning the input layer at an upper layer, excluding the top one.

We evaluated the light-energy efficiency of DC using the following definition: Energy efficiency=∑∀[O[|wK+1|2]]|l=9,f=1PxPy.(26)Here, the denominator represents the total input energy to the optical cascade. The numerator is the total energy on the output area of interest, calculated when the logic operation is configured to produce one output (l=9) and all elements of the input pair f are set to 1. The energy efficiency was assessed with respect to the scaling factor a and the width of the buffer t.

The light-energy efficiency is associated with the scaling factor a, which amplifies or attenuates the signals captured by the image sensor before the binarization process. A larger a indicates lower energy efficiency and vice versa. In the above demonstrations and analyses, a was included in the optimized parameters, as shown in Eq. (20). Here, a was set to a specific value and was not updated during the optimization process. Once the optimizations of the illumination pattern rl and the DOEs ϕk were completed, the energy efficiency in Eq. (26) and the computational error were calculated. This process was repeated by changing a from 2 to 32. The relationship between the energy efficiency and the computational error is shown in Fig. 11. The RMSEs for the energy efficiencies between 1.81% and 8.71% were less than 2.38×10−3. Therefore, nearly error-free calculation was achieved within this range of energy efficiencies.

The primary sources of energy loss were amplitude modulation on the illumination plane, light leakage from the optical cascade, and the cropping of the limited square area by the image sensor at the end of the optical cascade. The first issue can be solved by employing phase modulation on the illumination plane, although its modulation speed is lower than that of amplitude modulation on currently available SLMs. The second issue may be alleviated by reducing the intervals between layers. The third issue can be addressed by increasing the sensor area, employing anisotropic sampling, or utilizing anamorphic imaging. Another approach to improve energy efficiency is to increase the width of the buffer, as indicated in the next section. The trade-off between energy efficiency and computational error will not be an issue in a proof-of-concept experimental demonstration with an optical setup, such as those shown in Sec. 7, by increasing the illumination intensity. However, this issue must be considered in practical applications, where energy efficiency in computation is a crucial factor.

The buffer t was introduced into DC to compensate for the light intensities transmitted or blocked by the input pair. It was expected to eliminate the computational encoding and decoding processes employed in previous methods for optical logic operations, including the SC scheme. In the above demonstrations and analyses, the buffer width was set to 16 pixels. The plots in Fig. 12 show the energy efficiencies and computational errors at different buffer widths, including zero width. In this analysis, the scaling factor a was included in the optimization parameters. This result supported the necessity of the buffer for error-free calculation. Furthermore, a larger buffer width increased the energy efficiency.

The RMSE for the logic operations at 1≤l≤8 without the buffer was reduced from 4.24×10−2 to 0 by adding a buffer of one pixel. On the other hand, the RMSE for the logic operations at 9≤l≤16 with no buffer was significantly improved from 4.40×10−1 to 0 by adding a one-pixel buffer. As shown in Table 1, operations at 1≤l≤8 do not include the operation with an input of fleft=0,fright=0 and an output of g^l=1. Conversely, the operations at 9≤l≤16 include such an operation. This result also verified the role of the buffer—compensating for the balance between the light intensities of the input and output in the optical cascade.

An issue in the physical demonstration of DC will be alignment errors. The system’s performance under alignment errors along the x and z axes is presented in Fig. 13, showing the computational error with one-dimensional alignment on the individual layers, including the illumination and input layers. The alignment error along the y axis was omitted in this analysis because its impact is considered similar to that along the x axis due to their symmetry. As shown in these results, the impact of the alignment error along the x axis was greater than that along the z axis.

Several methods for compensating for alignment errors in DNNs have been proposed, and these can be applied to configure our setup. The first approach is enhancing robustness against alignment errors or model errors by introducing them during the computational training process.65 The second approach is using a closed-loop process to feed back alignment errors or model mismatches to controllable optical elements, such as SLMs.66^,67 The third approach is incorporating integrated chip fabrication techniques, which significantly reduce alignment errors or model mismatches.32^,43

Two candidate experimental setups for DC are presented in Fig. 14. Both setups employ DMDs for the reconfigurable illumination and input due to the high speed and high contrast in DMD modulation. The first setup, shown in Fig. 14(a), uses transmissive phase modulation elements, such as DOEs. While it can be bulky, it is easier to align optical components. The polarization state of the light may optionally be controlled to prevent stray light from the DMDs. This type of setup has been demonstrated in DNNs for object classification and classical or quantum logic gates.28^,31^,41^,46 The second setup, shown in Fig. 14(b), uses a mirror and reflective phase modulation elements, such as SLMs. This reflective setup may be more compact and compatible with the closed-loop approach described in Sec. 6.6 to compensate for alignment errors. The diagonal propagation process can be considered when designing the phase modulations using rotational transformation in numerical diffraction.68 This type of reflective setup has been demonstrated in DNNs for a beam mode converter, a quantum gate, and optical reservoir computing.69^–71

Ryosuke Mashiko is a graduate student in the Department of Information Physics and Computing at the Graduate School of Information Science and Technology, the University of Tokyo, Tokyo, Japan. He received his BE degree in engineering from the University of Tokyo, in 2023. His work focuses on the development of photonic computing and computational imaging.

Makoto Naruse was a professor in the Department of Information Physics and Computing, Graduate School of Information Science and Technology, the University of Tokyo, Tokyo, Japan. He received his BE, ME, and PhD degrees in engineering from the University of Tokyo, in 1994, 1996, and 1999, respectively.

Ryoichi Horisaki is an associate professor in the Department of Information Physics and Computing at the Graduate School of Information Science and Technology, the University of Tokyo, Tokyo, Japan. He received his BS degree in engineering from Nara National College of Technology in 2005, and his MS and PhD degrees in information science from Osaka University in 2007 and 2010, respectively. His research interests include information photonics and computational imaging.