Integrated photonic modular arithmetic processor

Yuepeng Wu; Hongxiang Guo; Bowen Zhang; Jifang Qiu; Zhisheng Yang; Jian Wu

doi:10.1364/PRJ.527762

1. INTRODUCTION

Since the breakdown of Dennard scaling [1], the quest for faster and more energy-efficient computing units has been met with significant challenges. A prevailing consequence has been the limitation of current processors in clock frequencies and utilization [2]. Stemming from inherent physical problems faced by CMOS transistor technology, it has resulted in computing performance being a major bottleneck for numerous potential applications [3]. Efforts have therefore been attempted to enhance the conventional transistor-based computing paradigm with alternative platforms. Among these, promising advances in the energy efficiency of integrated optoelectronic devices and their compatibility with CMOS [4 –7] have led to an increased interest in integrated photonic computing, which allows operations at unprecedented bandwidths [8].

Most published works on integrated photonic computing employ intensity as the “calculation quantity”, as illustrated in Fig. 1(a), encompassing both the digital and the analog types. The former, conducting bit-wise operations with optical logic gates, enables superior performance to their electric counterparts [9,10]. However, optical intensity signals suffer losses from both the material absorption and the intrinsic property of non-reciprocal Boolean operation [11], making it challenging to be cascaded to form a photonic arithmetic unit with a high bit-width [12] using photonic digital computing architectures.

Figure 1.(a) General structure of emerging photonic computing. The digital-system-compatible and efficient calculation is performed by exploiting converters and the intrinsic alignment between a controllable physical phenomenon and a specific arithmetic method. (b) Overview of residue number system. (c) Schematic diagram of the phase-based photonic modular arithmetic processor (PPMAP) architecture. (d) Mapping between operands and phase when taking modulus $m_{i} = 12$ as an example, along with a demonstration of basic modular arithmetic performed based on this mapping.

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Photonic analog computing, on the other hand, utilizes the manipulation of optical analog quantities to efficiently execute algebraic operations. Substantial advancements in intensity-based photonic analog computing have been made in conducting operations, such as matrix multiplication [13 –15], convolution operations [16 –18], and neural network model inference [19 –21]. Despite the successes of analog photonic computing in several domains, these architectures are generally optimized for low-precision operations and applications that can tolerate high noise levels. This optimization limits the ability to fully leverage the flexibility and efficiency of analog signals to meet the broader demands of wider application domains. Consequently, the development of an analog-based photonic arithmetic processor architecture with higher and scalable precision becomes imperative.

However, utilizing analog optical signals for high-precision computations faces two primary challenges. First, optical signals themselves inherently exhibit lower precision. The analog intensity signal is susceptible to noise, which limits its calculation precision due to a relatively poor signal-to-noise ratio (SNR) [22]. The calculation precision of published works (usually 4–5 bits [23,24]) falls short of meeting general requirements, with no efficient method available to improve their calculation precision as compared to digital computation systems [25,26]. Second, the mandatory use of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) incurs additional costs and confinements. A photonic analog computing system operating at ultra-high bandwidth necessitates high-precision ADCs and DACs matching its speed. This requirement poses a significant challenge as there is a well-known tradeoff between bandwidth and resolution for the electric AD/DA converters [27,28], while also posing significant energy consumption overhead [29,30] to the integrated photonic computing system. These “precision challenge” and “converter challenge” have hindered the practical implementation of the intensity-based methods and have necessitated the pursuit of alternative solutions for integrated photonic computing.

Phase is another controllable physical quantity in integrated photonics apart from the intensity and has not yet been fully explored in the field of photonic computing, which can be controlled more efficiently by an integrated phase modulator (PM) [31,32] and exhibiting intrinsic periodicity. That feature of the optical phase aligns naturally with the modular arithmetic in which numbers are folded by a specific modulus [33,34]. For modulus arithmetic, leveraging a non-traditional numerical representation format, i.e., residue number system (RNS), allows for the decomposition of high-precision computations into multiple parallel low-precision operations, as depicted in Fig. 1(b). The correspondence between the modular arithmetic and the optical phase opens up an avenue for the efficient extension of calculation precision in integrated photonic computing systems [35]. Meanwhile, representing information in the phase domain offers the opportunity to alleviate the dependence on electric AD/DA converters through the design of optical counterparts. In this paper, we propose an integrated phase-based photonic modular arithmetic processor (PPMAP) architecture aimed at addressing the precision and converter challenges prevalent in photonic computing. Utilizing the unique characteristics of phase, its components, PPMAP units, enable accurate execution of basic modular arithmetic operations and support multi-operand operations, which is non-trivial for specialized accelerators [36]. The precision of this architecture can be effectively elevated using the RNS theory. In a proof-of-concept experiment, the three-unit PPMAP achieved 9-bit calculation precision, which is unprecedented for intensity-based photonic computing architecture. Moreover, based on the multi-operand characteristics of PPMAP architecture and our previous work on a phase-shifted optical quantizer [37,38], we demonstrate the accurate loading and extraction of information into and from the phase domain with the seamlessly integrated photonic conversion interfaces, which makes an advancement in eliminating the constraints of AD/DA converters. Further simulations on a 4-unit 15-bit PPMAP indicate comparable reliability to electronic processors under reachable SNR conditions.

2. PPMAP ARCHITECTURE

The basic structure of the PPMAP unit is depicted in Fig. 1(c). A beam splitter (BS) evenly splits the power of an incident monochromatic laser into two beams, which propagate through two separate paths. Each path is equipped with a set of cascaded phase modulators (PMs). Finally, the phase difference between the signals in the two paths is extracted by a phase-to-digital converter (PDC) linked at the end. Since both beams originate from the same laser source, in the absence of a voltage bias on the modulator, they exhibit a stable static phase difference denoted as $φ_{0}$ . When a voltage is applied to one of the modulators, it introduces a dynamic phase difference denoted as $Δ φ$ . In the case of simultaneously applying voltage to the PMs, the overall dynamic phase difference is the sum of their individual contributions.

To perform modular arithmetic operations under modulus $m$ , $m$ discrete phase points from the analog quantity $Δ φ \in [0,2 π)$ are designated to represent the $m$ elements in the set ${0, 1, 2, \dots, m - 1}$ . These points must include the phase of 0 as the identity element and be uniformly spaced with an interval of $2 π / m$ to satisfy the closure property, which ensures that the result of the addition operation remains within the same set [33]. Consequently, the integers in modulo $m$ are mapped to the discrete dynamic phase differences $Δ φ_{Z} = {0, 2 π / m, 4 π / m, \dots, 2 π - 2 π / m}$ . This mapping allows for modular addition or subtraction operations by loading operands into the corresponding phase modulators on the same or different paths, as shown in Fig. 1(d), which illustrates an example of $m = 12$ . To perform a modular addition operation with operands “10” and “7”, followed by subtraction with “3”, we regulate two PMs on the same path and one PM on the other path to induce phase changes of $5 π / 3$ , $7 π / 6$ , and $π / 2$ . The closure property allows us to derive the results once we identify the specific discrete phase points from $Δ φ_{Z}$ . The PDC then determines the resulting phase $Δ φ = | 7 π {/ 3 |}_{2 π} = π / 3$ , corresponding to the calculation result of “ $| 10 + 7 - {3 |}_{12} = 2$ ”. This efficient implementation of modular addition also enables modular multiplication, using the same structure but with the inclusion of an index-sum multiplication method [39] that performs modular multiplication via a simple modular addition and a table lookup operation (see Appendix G).

Additionally, by leveraging the theory of the residue number system (RNS), which represents the integer operand, denoted as $X$ , by its remainders of a set of pairwise coprime moduli ${m_{1}, \dots, m_{N}}$ , i.e., the RNS format, $X_{RNS} = X % {m_{1}, \dots, m_{N}} = {{| X |}_{m_{1}}, \dots, {| X |}_{m_{N}}},$ (1)the original operation with high bit-width operands can be broken into multiple parallel modular arithmetic operations with much lower bit-width operands and different moduli, as long as the result is within the range $M = \prod_{i = 1}^{N} m_{i}$ . By orchestrating multiple PPMAP units with different moduli according to the RNS theory, as shown in Fig. 1(c), we construct the PPMAP architecture with a bit-width of $⌊ \log_{2} \prod_{i = 1}^{N} m_{i} ⌋$ , thereby realizing calculation with scalable precision.

3. RESULTS

A. High-Precision Integrated Photonic Calculation

Figures 2(a) and 2(b), respectively, illustrate the experimental setup and the integrated photonic chip utilized for the proof-of-concept experiments. The latter was fabricated on an SOI platform and corresponds to the fundamental structure depicted in Fig. 1(c). A continuous wave (CW) laser is coupled into the integrated waveguide through a grating coupler and is evenly separated via a subsequent $1 \times 2$ multimode interferometer (MMI). Those two laser beams then traverse two adjacent waveguides where four PMs load operands into the produced phase difference. The magnitude of the phase difference induced by a specific voltage value applied to the PM can be precisely controlled by the method described in Appendix B. Then, the two laser beams with a phase difference carrying the calculation result of those operands enter into a $2 \times K$ MMI to identify and quantify phase information. Figure 2(c) displays a micrograph of the MMI-structured optical PDC (OPDC) with five output channels (i.e., $K = 5$ ), where the two input laser beams take place with interference based on the self-imaging effect [40]. That makes the optical power at each output channel capture different profiles of the phase information $Δ φ$ . The relationship between the phase changes induced by varied control voltages applied to a modulator, PM0 [as depicted in Fig. 2(d)] and the optical power of the five channels is shown in Fig. 2(e). By performing threshold decision on the optical power signal of a channel using comparators, the 360-deg phase range is divided into multiple phase intervals. This division occurs due to a change in the binary codewords (0s and 1s) generated by that channel. By performing one decision on each channel’s optical power, the phase range can be divided into up to $2 K$ intervals. The specific phase interval in which the current phase lies can be determined according to the resulting Gray code digital output [41], as shown in Fig. 2(c) for the case of $m = 10$ . To discern the phase-encoded information accurately, we introduce an additional static phase bias $φ_{b}$ and pre-optimize it along with the decision thresholds for any modulus $m \leq 2 K$ (see Appendix C).

Figure 2.Phase manipulation on the integrated chip. (a) Schematic diagram of the experimental setup. PCB, printed circuit board; MVS, multi-channel voltage source; MPM, multi-channel optical power meter. (b) Micrograph of the integrated photonic chip and (c) MMI-structured OPDC, with five output channels. (d) The relationship between the voltage applied to PM0 and the magnitude of consequential phase change, and (e) the corresponding normalized optical power of the output signals. The zero phase reference point is chosen as $φ_{b}$ , while the optical power signals from multiple channels were normalized relative to optimized thresholds, ensuring that all thresholds are aligned at 0.5 on the graph. (f) The multi-channel optical power signals along with their corresponding threshold decision results (red or green for zero or one, respectively) at each time slot, and (g) the phase signal reconstructed from the optical power signals.

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Figures 2(d)–2(g) illustrate the experimental process of the loading and extracting phase information for the case of $m = 10$ . The voltages corresponding to different discrete phases in $φ_{b} + Δ φ_{Z}$ are applied to the modulator in varying time slots. By recovering the phase value from the multiple-channel optical power signals in Fig. 2(f), it can be observed that the phase is controlled to be in the middle of the expected phase intervals, as shown in Fig. 2(g). Furthermore, based on the digital results of the threshold decision to the optical power of multiple channels, which was simulated on the host computer in this experiment, we were able to accurately obtain the integer value corresponding to each specific discrete phase for every time slot.

The methods of phase information loading and extraction described above can be applied to various moduli, affording the flexibility to instantiate the PPMAP units corresponding to different moduli using a single integrated photonic device.

To demonstrate the superior calculation precision and process of our PPMAP architecture, we conducted experimental demonstrations of a 9-bit three-operand addition operation using moduli {10, 9, 7}. During the experiment, the same physical PPMAP unit depicted in Fig. 2 performed all the calculations involving different moduli, i.e., implementing three PPMAP units utilized one device via time division multiplexing. Seven sets of independent operand samples were selected and each underwent the operation of $A + B + C$ and the bit-width of the binary operands is $⌊ \log_{2} (10 \times 9 \times 7) ⌋ = 9$ . After converting into RNS format, the original multi-operand addition operation transformed into three corresponding modular arithmetic operations with varying moduli of {10, 9, 7}.

For each specific modulus, the operations on different sample sets perform consecutively at varying time slots. For implementing the operation of a single set in the phase domain, we simultaneously apply the voltages corresponding to the converted operands to multiple PMs. As shown in Fig. 3(b), we apply a constant voltage to PM0 to assign it the responsibility of providing the bias phase $φ_{b}$ . PM1, PM2, and PM3 are also assigned to accurately map operands A, B, and C to their respective phase change amounts. The mapping method for $m = 9$ is illustrated in Fig. 3(f) as an example. The applied voltage signals and their consequent calculation results in the phase domain are illustrated in Figs. 3(c) and 3(d). For a specific time slot, the phase values fall within the phase interval corresponding to the exact computed results, thus achieving the desired calculations in the phase domain. Figure 3(e) displays the integer signals generated by the OPDC, which infers the precise extraction of the RNS-format calculation results from the phase domain.

Figure 3.Demonstration of PPMAP for algebraic operation (a) Schematic of the PPMAP architecture in the demonstration experiment, which contains three units. (b) The operand or function assigned to each modulator. (c)–(e) The parallel photonics-accelerated modular arithmetic operations in moduli {10, 9, 7}. In different time slots, applying (c) voltage signals corresponding to RNS-formatted operands to the modulators to perform operations on different sample sets, resulting in (d) output phase signals and (e) quantized results obtained from the OPDC. (f) The method of mapping operands to corresponding phases: since $φ_{b}$ has been provided by PM0, we directly control the voltage of PM2 to induce a phase change of $Δ φ_{X} = X \cdot 2 π / m$ for operand $X$ and control the voltage of PM1 and PM3 to generate a phase change equal to $2 π - Δ φ_{X}$ when mapping X to phase $Δ φ_{X}$ .

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When the result is obtained in RNS format, a non-positional and multiple-radix number system, the PPMAP successfully completes a high-precision arithmetic operation. Although the outcomes are represented differently from the binary format, which is a positional and single-radix number system, they are both valid results of the same operation [34]. To clearly demonstrate that the PPMAP has performed the correct calculation, we convert the RNS format into conventional notations on an electronic processor. In Fig. 3(g), we illustrate the process of the Chinese Remainder Theorem (CRT) algorithm, a basic method for the format conversion. Here, $M = Π_{i = 1}^{N} m_{i}$ , $M_{i} = M / m_{i}$ , and ${| \cdot |}_{m_{i}}^{- 1}$ represents the modular multiplicative inverse, ensuring that $| {| M_{i} |}_{m_{i}}^{- 1} \cdot M_{i} |_{m_{i}} \equiv 1$ . The RNS results from the photonic processor and the binary results from the electronic one are consistent, except for the result in set5. This discrepancy occurs because the computation in set5 produces a result that exceeds the valid range of [0, 630], leading to a numerical overflow that warped 835 to ${| 835 |}_{630} = 205$ . It should be emphasized that format conversion is not obligatory for performing actual computing tasks. Recent advances in computer architecture have confirmed that all computer components efficiently function within the RNS format [42], and computing architectures built on the RNS format can perform a variety of applications, such as matrix multiplication, fast Fourier transform, and combinatorial optimization, without frequent format conversion [43].

While our initial proof-of-concept experiment employed thermo-optic modulators on an SOI platform at a moderate speed, it is crucial to highlight the adaptability of the proposed PPMAP architecture across diverse platforms. For instance, when implemented using electro-optic modulators on a commercially available thin-film lithium niobate platform, the PPMAP architecture seamlessly achieves high-precision calculation with bandwidths extending into the range of several tens of GHz [38].

B. Optical Digital-to-Phase Converters

The thorough resolution of the “converter challenge” necessitates not only the OPDC but also dedicated electronic-photonic DAC modules that effectively convert digital operands into the analog phase domain. As a DAC essentially performs a weighted summation with fixed weight on a digital operand, denoted as $X$ , and concurrently transfers the result into analog quantity $Ψ$ , $X = {(x_{L - 1} x_{L - 2} \dots x_{0})}_{2} \to Ψ_{X} (\sum_{i = 0}^{L - 1} 2^{i} x_{i}),$ (2)where $x_{i} = 0$ or 1, and $L$ represents the bit-width of $X$ , we can leverage the just-demonstrated multi-operand feature of PPMAP architecture to implement the optical digital-to-phase converter (ODPC).

An ODPC comprises a collection of PMs positioned along the paths of the PPMAP unit. It receives the digital signal of one operand from the parallel bus. In the basic design of the ODPC, it is equipped with $L$ PMs that are controlled by each binary digit $x_{i}$ in the $X$ . Each PM in the ODPC is engineered to exhibit a specific phase response to the voltage amplitude of the digital signal. In particular, when the phase response of the $i$ th PM is designed as $Δ φ_{i} = 2 π {| 2}^{i} |_{m} / m$ , the OPDC enables the direct transformation of the $L$ synchronously applied digital signal into the resulting summation in the phase domain: $Δ φ_{X} = \sum_{i = 0}^{L - 1} x_{i} Δ φ_{i} = \sum_{i = 0}^{L - 1} x_{i} {| 2}^{i} |_{m} \frac{2 π}{m} = \frac{2 π}{m} \sum_{i = 0}^{L - 1} {| 2}^{i} x_{i} |_{m} = \frac{2 π}{m} {| X |}_{m} .$ (3)

When the digital operand is in RNS format, satisfying $X < m$ , the OPDC produces the phase value $Δ φ = 2 π X / m$ , performing the role of a DAC in the phase domain. Furthermore, when the digital operand $X$ exceeds the modulus $m$ , the ODPC performs the digital-to-analog conversion and the format conversion simultaneously.

The experimental demonstration of a 4-bit ODPC along with an OPDC, as shown in Fig. 4, validated the successful operation of this photonic conversion interface. During this experiment, digital operands representing 4-bit binary codes ranging from 0 to 15 were sequentially fed into the corresponding phase modulators PM0, PM1, PM2, and PM3. With $m = 7$ , all modulators generated phase changes of 0 or $2 π {| 2}^{i} |_{7} / 7$ based on the values of the digital signals (0 or 1) at each bit position $i$ , while PM0 provided an additional bias phase $φ_{b}$ simultaneously. The experimental results show that the OPDC successfully performed the modulo-7 remainder calculation on the 4-bit binary operands and accurately transferred the results to analog phase values.

Figure 4.Feasibility verification of the photonic conversion interface. This experiment demonstrates a PPMAP unit with $m = 7$ consisting of one OPDC and one 4-bit ODPC. Four PMs are controlled by four parallel digital signals and convert the 4-bit operands into phases. In this proof-of-concept experiment, the digital signals are scaled corresponding to the bit position to produce the expected phase change.

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In the generalized ODPC design, low-bit-width DACs are utilized to achieve a larger overall bit-width (see Appendix D). As integrated intensity modulators, like microring resonators, exhibit poor linearity, achieving mapping of operands with a given precision into transmissivities necessitates the DAC with higher precision [44]. In contrast, the favorable linearity and the characteristics of phase modulation enable the decomposition of high-precision DAC tasks into $G$ parallel low-bit-width tasks, which can reduce power consumption and delays, from $O (e^{L})$ to $O (G \cdot e^{L / G})$ and $O (e^{L / G})$ [30], endowing the PPMAP for more efficient processing capabilities.

4. DISCUSSION

A. Precision and Reliability

The PPMAP architecture offers superior calculation precision compared to intensity-based photonic computing methods. While intensity-based methods heavily rely on the system’s SNR for calculation precision, PPMAP leverages the RNS theory to distribute the calculation precision across multiple physical implementations. This decomposition substantially reduces the dependence on SNR and enables a relatively high calculation precision. Section 3.A has demonstrated the superior calculation precision of PPMAP (9 bits) compared to intensity-based methods. Now, the focus is on further analyzing the impact of noise on both approaches by conducting simulations to compare their performance in a given 15-bit multiplication scenario.

Figure 5.Analysis on precision and reliability. (a) The relative calculation error of PPMAP and intensity-based optical computing methods in simulating a 15-bit multiplication task under varying SNR levels. (b) The relative frequency of errors obtained from simulation results for PPMAP, along with its probability model.

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To further quantify the reliability of the PPMAP architecture, a probability model [Eq. (4)] was developed (detailed in Appendix E): $P = 1 - \prod_{i = 1}^{N} \prod_{j = 1}^{K_{i}} \frac{1}{2} (1 + \erf (\frac{\sqrt{3} \sin (\frac{π}{K_{i}} (j - \frac{1}{2}))}{2 \sqrt{2} \cdot 10^{- \frac{SNR}{20}}})) .$ (4)

As shown in Fig. 5(b), the predicted probabilities of system errors at different SNR levels aligned well with the simulated relative frequency of errors. With the addition of computational error correction mechanisms, such as triple modular redundancy (TMR) [47], the error probability P can be reduced to impressively low levels. For example, with an SNR of approximately 34 dB and employing TMR, the system can achieve an error probability as low as $3 P^{2} - 2 P^{3} \approx 3 \times 10^{- 20}$ [48], indicating a mean time between failure (MTBF) [49] of around 10 years when continuously operating at a frequency of 100 GHz. This level of reliability is comparable with commercial electronic processors [50], which makes PPMAP a promising candidate for performing high-precision and reliable computation tasks.

In high-speed scenarios, the PPMAP system demands high-quality modulators and detectors to maintain a sufficiently high SNR at elevated bandwidths. This contributes to reducing the overall error probability and supporting more modulus values $m$ , further enhancing calculation precision.

B. Computational Efficiency and Scalability

As analyzed in the previous section, the RNS-based PPMAP architecture overcomes the precision limitations of current photonic computing systems. However, it is essential to analyze whether this high precision is achieved at the cost of significantly reduced computational efficiency and scalability. To address this concern, we conducted a qualitative comparison between the PPMAP architecture and other recent optical computing architectures. We analyzed the computational volume (i.e., the equivalent number of basic operations the system executes per symbol period) and system overhead [including the number of required transmitters (Tx) and receivers (Rx), which respectively consist of modulators/detectors, DACs/ADCs, etc.] as functions of the scale factor $D$ (or $D_{1} D_{2}$ ).

As shown in Table 1, the computational volume and system overhead for optical computing architectures, including PPMAP, increase linearly with the system scale. Compared to other architectures, PPMAP reduces computational volume by up to approximately 50%, while the system overhead does not exceed $N$ times that of the architecture with the minimal overhead. This indicates that, regardless of system scale, PPMAP achieves a linear improvement in precision relative to $N$ with no more than a $2 N$ decrease in computational efficiency. This ensures that the PPMAP architecture maintains computational efficiency comparable to other photonic computing methods while also providing scalability consistent with other integrated solutions.

Therefore, for general-purpose computing, PPMAP can serve as a high-speed general-purpose processor with high computational efficiency, executing basic arithmetic operations to accelerate various tasks. For application-specific tasks, PPMAP’s scalability allows for tailored designs to further enhance efficiency.

C. Optoelectronic Signal Converters

Despite the use of moderate bandwidth in the experimental demonstration, the implementation of ODPC/OPDC addresses the performance challenges encountered by electronic signal converters in high-speed, high-precision optical computing applications. This is attributed to the unique characteristics of the optical system employed by ODPC/OPDC, which decompose a single high-precision ADC or DAC task into multiple parallel low-precision tasks, such as codeword decision or digital modulation.

This decomposition is pivotal as it breaks the precision-speed tradeoff constraint inherent to electronic signal converters, enabling optoelectronic converters to process high-precision signals at low-precision conversion speeds. Moreover, with recent advancements in the performance of integrated photonic devices [51,52], the current analog bandwidth limitations [29] can be alleviated by incorporating optoelectronic devices. The proposed OPDC/ODPC architectures adopt an integrated design compatible with existing digital systems. By leveraging advanced optoelectronic packaging and fabrication techniques [53], these specially designed optoelectronic signal converters can outperform conventional off-the-shelf electronic signal converters.

5. CONCLUSION

We have proposed PPMAP, an integrated photonic computing architecture that performs modular arithmetic based on the optical phase and RNS. The architecture is capable of addition, subtraction, and multiplication and supports multi-operand operations. PPMAP can achieve relatively high precision, and a 9-bit calculation was experimentally demonstrated. Further simulation extends its calculation precision to 15 bits and indicates that its reliability can approach the level of commercial processors under the SNR condition of 34 dB when fortified with error correction mechanisms. Additionally, this architecture harmoniously integrates our proposed ODPC and OPDC, proposing a solution to the long-standing constraints instituted by electronic AD/DA interfaces in photonic computing, and an experimental demonstration confirms the feasibility of this photonic conversion interface. Future research will explore the integration of higher-performance integrated photonic devices into the functional modules of PPMAP to improve the system’s calculation precision in high-speed scenarios.

Category: Integrated Optics

Received: Apr. 22, 2024

Accepted: Sep. 2, 2024

Published Online: Nov. 1, 2024

The Author Email: Hongxiang Guo (hxguo@bupt.edu.cn), Jian Wu (jianwu@bupt.edu.cn)

DOI:10.1364/PRJ.527762