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Laser & Optoelectronics Progress, Volume. 61, Issue 19, 1913023(2024)

High-Resolution Digital LCoS Chip Design with Selectable Refresh Mode

Chenye Wei1,2, Li Tian1、*, Yingqi Feng1, and Yongxin Zhu1
Author Affiliations
  • 1Research and Development Center of Smart Information and Communications Technologies, Shanghai Advanced Research Institute, Chinese Academy of Sciences, Shanghai 201210, China
  • 2University of Chinese Academy of Sciences, Beijing 100049, China
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    AbstractGet PDF(in Chinese)
    Figures&Tables (12)
    Equations (1)
    References (17)
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    Figures & Tables(12)
    Data set (valid illumination) period of each subframe

    Fig. 1. Data set (valid illumination) period of each subframe

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    Logic block diagram of LCoS driver architecture

    Fig. 2. Logic block diagram of LCoS driver architecture

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    Block diagram of structure of a single pixel

    Fig. 3. Block diagram of structure of a single pixel

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    Layout of 2×2 pixel unit

    Fig. 4. Layout of 2×2 pixel unit

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    LVDS (single) interface signal timing diagram

    Fig. 5. LVDS (single) interface signal timing diagram

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    Schematic block diagram of data driver bus interface

    Fig. 6. Schematic block diagram of data driver bus interface

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    Block diagram of the row scan interface circuit

    Fig. 7. Block diagram of the row scan interface circuit

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    Simulation results of pixel circuit. (a) Progressive refresh mode; (b) global refresh mode

    Fig. 8. Simulation results of pixel circuit. (a) Progressive refresh mode; (b) global refresh mode

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    Schematic block diagram of verification test system

    Fig. 9. Schematic block diagram of verification test system

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    Photo of verification test system

    Fig. 10. Photo of verification test system

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    Measured data and control signal waveform of LCoS chip simulator

    Fig. 11. Measured data and control signal waveform of LCoS chip simulator

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    • Table 1. Comparison of key indicators between this design and results of other papers

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      Table 1. Comparison of key indicators between this design and results of other papers

      Key indicatorThis designJDT'12［15］TCAS I'20［11］MJ'23［13］PIDW'20［12］JSID'05［10］
      Tech. node /nm180180130180180—
      Pixel topology9T6T8T11T——
      Resolution3840×2160854×480100×2001632×16321920×10801280×720
      Gray scale /bit10.08.08.09.6—8.0
      Voltage /V1.81.8/3.31.5/3.3———
      Frame rate /Hz6036036060—180
      Pixel size /（μm×μm）5.5×3.5—5.2×5.26×34.5×4.512.0×12.0
      Frequency /MHz272.6302.5100.0125.0——
      Refresh modeProgressive/globalProgressiveProgressiveProgressiveGlobalGlobal
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    Chenye Wei, Li Tian, Yingqi Feng, Yongxin Zhu. High-Resolution Digital LCoS Chip Design with Selectable Refresh Mode[J]. Laser & Optoelectronics Progress, 2024, 61(19): 1913023

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    Paper Information

    Category: Integrated Optics

    Received: Jan. 26, 2024

    Accepted: Mar. 18, 2024

    Published Online: Oct. 16, 2024

    The Author Email: Li Tian (tianl@sari.ac.cn)

    DOI:10.3788/LOP240620

    CSTR:32186.14.LOP240620

    Topics

    laser devices and laser physics
    Lasers and Laser Optics
    Laser physics
    laser manufacturing
    Instrumentation, Measurement and Metrology