Laser & Infrared, Volume. 55, Issue 3, 388(2025)
A phase-locked loop design for high-speed readout circuits
[2] [2] YU ZHAO, BEHZAD RAZAVI. Phase noise integration limits for jitter calculation[C]//2022 IEEE International Symposium on Circuits and Systems (ISCAS 2022), 2022: 1005-1008.
[3] [3] DONGIN KIM, SEONGHWAN CHO. A supply noise insensitive PLL with a Rail-to-rail swing ring oscillator and a wideband noise suppression loop[C]//2017 Symposium on VLSI Circuits, 2017: 134-135.
[4] [4] ABDULAZIZ, MOHAMMED, FORSBERG, et al. A 10 mW mm-wave phase-locked loop with improved lock time in 28 nm FD-SOI CMOS[J]. IEEE Transactions on Microwave Theory and Techniques, 2019, 67(4): 1588-1600.
[5] [5] LEVANTINO, S., MARZIN, G., SAMORI, C., et al. A wideband fractional-N PLL with suppressed charge-pump noise and automatic loop filter calibration[J]. IEEE Journal of Solid-State Circuits, 2013, 48(10): 2419-2429.
[6] [6] NITIN KUMAR, MANOJ KUMAR. Design of CMOS-based low-power high-frequency differential ring VCO[J]. Internationaljournal of electronicsletters, 2019, 7(2): 143-153.
[7] [7] WENFENG LOU, XIAODONG LIU, PENG FENG, et al. An integrated 0.38-6 GHz, 9-12 GHz fully differential fractional-N frequency synthesizer for multi-standard reconfigurable MIMO communication application[J]. Analog Integrated Circuits and Signal Processing, 2014, 78(3): 807-817.
Get Citation
Copy Citation Text
FANG Kai, DONG Rui-qing, LI Jing-guo. A phase-locked loop design for high-speed readout circuits[J]. Laser & Infrared, 2025, 55(3): 388
Category:
Received: Jul. 10, 2024
Accepted: Apr. 23, 2025
Published Online: Apr. 23, 2025
The Author Email: LI Jing-guo (lijg@live.com)