Fig. 1. Framework of the synchronizing system with high resolution and low jitter

Fig. 2. Encoding and decoding of the reference clock and delayed start signal

Fig. 3. Principle of coarse delay by using transceiver

Fig. 4. Transceiver configured in Basic (PMA Direct)

Fig. 5. Principle of fine delay by using stripline delay line

Fig. 6. Wave of the transceiver implementing the coarse delay of the synchronization signal

Fig. 7. Codec timing logic simulation of the reference clock and delayed start signal

Fig. 8. Generation of the waveform data for synchronous signals with coarse delay

Fig. 9. Simulation of key circuits on the board

Fig. 10. Framework of experimental test system

Fig. 11. Timing jitter result of synchronous signals