Fig. 1. Schematic diagram of ROI readout function

Fig. 2. Relationship between total data volume and readout time and ROI size

Fig. 3. Change of frame rate with ROI size

Fig. 4. 3-8 decoder structure

Fig. 5. Race and hazard phenomenon and solution

Fig. 6. Gray code decoder architecture

Fig. 7. Single pixel control word architecture

Fig. 8. Control circuit and memory

Fig. 9. Subarray control word architecture

Fig. 10. Control modules and storage units in subarray

Fig. 11. ROI of readout integrated circuitr

Fig. 12. Comparison of control word writing time

Fig. 13. Control sub circuit

Fig. 14. Process of control word writing

Fig. 15. Diagram of control word writing sequence

Fig. 16. Process of row selection

Fig. 17. Row selection sequence diagram

Fig. 18. Row select circuit and control circuit layout

Fig. 19. Simulation waveform

Fig. 20. Simulation result