Microelectronics, Volume. 52, Issue 1, 77(2022)

A Novel Latch-Immune LDMOS for High-Voltage Protection

SUN Haonan, WANG Junchao, LI Haoliang, and ZHANG Yingtao
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    References(6)

    [2] [2] ZHANG H P, LIANG Z, WANG D J, et al. Negative ESD robustness of a novel anti-ESD TGFPTD SOI LDMOS [C] // ICCAIE. Kuala Lumpur, Malaysia. 2011: 1-4.

    [3] [3] CHEN W Y, KER M D. New layout arrangement to improve ESD robustness of large-array high-voltage nLDMOS [J]. IEEE Elec Dev Lett, 2010, 31(2): 159-161.

    [8] [8] JIN X L, WANG Y, ZHONG Z Y. Optimization of LDMOS-SCR device for ESD protection based on 0.5 μm CMOS process [C] // 12th EMC Compo. Hangzhou, China. 2019.

    [9] [9] FAN H, JIANG L, ZHANG B. A method to prevent strong snapback in LDNMOS for ESD protection [J]. IEEE Trans Dev Mater Reliab, 2013, 13(1): 50-53.

    [10] [10] YE R, LIU S Y, DAI Z G, et al. ESD failure analysis and robustness improvement for multi-STI-finger LDMOS used as output device [C] // IEEE 30th ISPSD. Chicago, IL, USA. 2018: 339-342.

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    SUN Haonan, WANG Junchao, LI Haoliang, ZHANG Yingtao. A Novel Latch-Immune LDMOS for High-Voltage Protection[J]. Microelectronics, 2022, 52(1): 77

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    Paper Information

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    Received: Mar. 15, 2021

    Accepted: --

    Published Online: Jun. 14, 2022

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.210103

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