Real-Time OFDR Processing Technology Based on Low Error Parallel Computing Acceleration

Luwei Shuai; Liuxin Zhang; Lei Ye; Zhaoyong Wang; Kan Gao; Qing Ye

doi:10.3788/CJL231526

Chinese Journal of Lasers, Volume. 51, Issue 14, 1406006(2024)

Real-Time OFDR Processing Technology Based on Low Error Parallel Computing Acceleration

Luwei Shuai^1,2, Liuxin Zhang^1,2, Lei Ye^1、*, Zhaoyong Wang^1,3, Kan Gao¹, and Qing Ye^1,2、**

¹Key Laboratory of Space Laser Communication and Detection Technology, Shanghai Institute of Optics and Fine Mechanics, Chinese Academy of Sciences, Shanghai 201800, China

²Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing 100049, China

³Shanghai Zhongke Shenguang Optoelecronic Industry Co., Ltd., Shanghai 201815, China

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Figures & Tables(15)

Fig. 1. OFDR basic optical path

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Fig. 2. The overall structure and FPGA internal architecture of a low-error parallel accelerated OFDR system

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Fig. 3. Signal flow diagram of low error parallel acceleration OFDR system

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Fig. 4. Schematic diagram of noise false triggering under single-threshold

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Fig. 5. Schematic diagram of no false triggering under double-threshold

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Fig. 6. Processing timing diagram under ping pong operation

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Fig. 7. Structure of a single-computing core

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Fig. 8. Rotation factor bit width versus calculation error

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Fig. 9. Effective signal ratio versus calculation error

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Fig. 10. Basic structure diagram of experimental platform

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Fig. 11. FPGA resource consumption chart

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Fig. 12. Comparison of calculation results. (a) Overall comparison of optical path; (b) comparison of reflection details

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Table 1. Comparison of spectral analysis algorithms

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Table 1. Comparison of spectral analysis algorithms

Characteristic	Fast Fourier transform	Chrip-Z transform	Wavelet transform	Discrete Fourier transform
Computational cost	Very low	High	Low	Very high
Point limit	Must 2^N	Must 2^N	None	None
Spectral analysis error	High （possible need to discard points or fill in zeros）	Low	Low （if selecting the appropriate mother wavelet）	Very low
Computational cumulative error	Low （error can be estimated）	High （error can not be estimated）	Low （error can be estimated）	Very low （error can be estimated）
Processor	CPU， GPU， DSP， FPGA	CPU， GPU	CPU， GPU	CPU， GPU， FPGA

Table 2. Logic truth table for double-threshold comparator
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Table 2. Logic truth table for double-threshold comparator
Input Q（n） Q（n+1）
X（n）>C_mp1 0 1
1 1
X（n）≤C_mp1 0 0
1 1
X（n）>C_mp2 0 0
1 1
X（n）≤C_mp2 0 0
1 0

Table 3. Comparison table for calculation time

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Table 3. Comparison table for calculation time

Round	Calculation time for500 points /ms		Calculation time for3000 points /ms
Round	FPGA	Computer	FPGA	Computer
Average	5.958	65.69	35.87	581.57
1^st	5.943	67.37	35.92	562.50
2^nd	5.954	62.03	35.87	597.89
3^rd	5.961	63.99	35.77	594.09
4^th	5.989	66.72	35.93	574.49
5^th	5.941	68.36	35.83	578.85

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Luwei Shuai, Liuxin Zhang, Lei Ye, Zhaoyong Wang, Kan Gao, Qing Ye. Real-Time OFDR Processing Technology Based on Low Error Parallel Computing Acceleration[J]. Chinese Journal of Lasers, 2024, 51(14): 1406006

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