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Chinese Journal of Liquid Crystals and Displays, Volume. 38, Issue 11, 1521(2023)

Design and implementation of convolution neural network accelerator for Winograd algorithm based on FPGA

Zhao-xu NIU1,2 and Hai-jiang SUN1,2、*
Author Affiliations
  • 1Changchun Institute of Optics，Fine Mechanics and Physics，Chinese Academy of Sciences，Changchun 130033，China
  • 2University of Chinese Academy of Sciences，Beijing 100049，China
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    AbstractGet PDF(in Chinese)
    Figures&Tables (18)
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    References (18)
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    Figures & Tables(18)
    Schematic diagram of Winograd convolution process

    Fig. 1. Schematic diagram of Winograd convolution process

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    Hardware architecture diagram of convolutional neural network accelerator

    Fig. 2. Hardware architecture diagram of convolutional neural network accelerator

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    Diagram of hardware quantification flow

    Fig. 3. Diagram of hardware quantification flow

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    Slice convolution flow chart

    Fig. 4. Slice convolution flow chart

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    Design drawing of feature data fusion

    Fig. 5. Design drawing of feature data fusion

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    Schematic diagram of input data buffer reuse module

    Fig. 6. Schematic diagram of input data buffer reuse module

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    Convolution design drawing of six stage assembly line

    Fig. 7. Convolution design drawing of six stage assembly line

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    Remote sensing image of river map

    Fig. 8. Remote sensing image of river map

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    Grayscale image of convolution output

    Fig. 9. Grayscale image of convolution output

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    Status diagram of data accumulation output module

    Fig. 10. Status diagram of data accumulation output module

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    Display diagram of image data stored in DDR memory

    Fig. 11. Display diagram of image data stored in DDR memory

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    ZCU104 hardware platform test diagram

    Fig. 12. ZCU104 hardware platform test diagram

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    Serial port output result diagram

    Fig. 13. Serial port output result diagram

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    • Table 1. Partial results after quantification of VGG-16 network

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      Table 1. Partial results after quantification of VGG-16 network

      层次缩放比例原权重量化后权重
      Conv1-1~Conv3-10.003 906 25-0.553 730 607 032 775 9-34
      Conv3-2~Conv4-30.001 953 125-0.030 606 031 417 846 68-9
      Conv5-1~Conv5-20.000 976 562 5-0.029 665 347 188 711 166-30
      Conv5-30.001 953 1250.027 768 215 164 542 19814
      Fc10.000 244 140 625-0.001 109 445 700 421 929 4-5
      Fc20.000 488 281 25-0.011 262 043 379 247 189-23
      Fc30.003 906 250.000 411 447 166 698 053 50

    • Table 2. Revised VGG-16 network structure table

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      Table 2. Revised VGG-16 network structure table

      层次输入尺寸输出尺寸操作数/G
      Conv1-1224×224×3224×224×640.173 4
      Conv1-2224×224×64224×224×643.699 3
      Conv2-1112×112×64112×112×1281.849 7
      Conv2-2112×112×128112×112×1283.699 3
      Conv3-156×56×12856×56×2561.849 7
      Conv3-256×56×25656×56×2563.699 3
      Conv3-356×56×25656×56×2563.699 3
      Conv4-128×28×25628×28×5121.849 7
      Conv4-228×28×51228×28×5123.699 3
      Conv4-328×28×51228×28×5123.699 3
      Conv5-114×14×51214×14×5120.924 8
      Conv5-214×14×51214×14×5120.924 8
      Conv5-314×14×51214×14×5120.924 8
      Fc17×7×5121×1×4 0960.205 5
      Fc21×1×4 0961×1×4 0960.033 6
      Fc31×1×4 0961×1×450.000 03
      累计——30.931 83

    • Table 3. Hardware resource usage

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      Table 3. Hardware resource usage

      片上资源总资源数占用资源数比例/%
      LUT230 400152 94366.38
      LUTRAM101 76068 15866.98
      FF460 80088 29619.16
      BRAM31217355.45
      URAM9696100
      DSP1 72851429.75

    • Table 4. Comparison of network accuracy after hardware implementation

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      Table 4. Comparison of network accuracy after hardware implementation

      网络大小/MBTOP-1 acc损失
      VGG-16（GPU）52779.4%
      VGG-16（FPGA）15178.6%0.8%

    • Table 5. Comparison with existing FPGA acceleration schemes

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      Table 5. Comparison with existing FPGA acceleration schemes

      VGG16加速文献［18］文献［17］文献［16］本文
      平台XC7VX485T

      Zynq

      XC7Z045

      Ultrascale

      KU060

      		ZCU104
      时钟/MHz100150200200
      数据精度8 bit16 bit16 bit8 bit
      DSP1 7967801 058514
      卷积层计算性能/GOPS758.19187.8310354.5
      计算效率/GOPS（DSP）0.4220.2410.2930.69
      功耗/W17.89.63259.04
      能效/（GOPS·W-1）42.5919.512.439.21
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    Zhao-xu NIU, Hai-jiang SUN. Design and implementation of convolution neural network accelerator for Winograd algorithm based on FPGA[J]. Chinese Journal of Liquid Crystals and Displays, 2023, 38(11): 1521

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    Paper Information

    Category: Research Articles

    Received: Jan. 13, 2023

    Accepted: --

    Published Online: Nov. 29, 2023

    The Author Email: Hai-jiang SUN (sunhaijing@126.com)

    DOI:10.37188/CJLCD.2023-0013

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