Chinese Optics Letters, Volume. 18, Issue 9, 090602(2020)

Digital-analog hybrid optical phase-lock loop for optical quadrature phase-shift keying

Shaowen Lu1,2,3、*, Yu Zhou1, Funan Zhu2,3, Jianfeng Sun1,2, Yan Yang3, Ren Zhu3, Shengnan Hu3, Xiaoxi Zhang3, Xiaolei Zhu1,2, Xia Hou2,3、**, and Weibiao Chen1,2
Author Affiliations
  • 1Key Laboratory of Space Laser Communication and Detection Technology, Shanghai Institute of Optics and Fine Mechanics, Chinese Academy of Sciences, Shanghai 201800, China
  • 2Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing 100049, China
  • 3Laboratory of Space Laser Engineering, Shanghai Institute of Optics and Fine Mechanics, Chinese Academy of Sciences, Shanghai 201800, China
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    Figures & Tables(10)
    Schematic of the QPSK fourth-power phase-lock loop.
    Principle of electro-optic modulation frequency shift as OVCO.
    Linear model of the analog fourth-power OPLL.
    Phase-error standard deviation versus loop natural frequency.
    Optimized natural frequency versus loop delay time.
    (a) Frequency fluctuation PSD of the transmitter (TX)/receiver (RX) laser and (b) the constellation of the QPSK modulation signal.
    QPSK fourth-power phase-lock loop simulation: (a) the Lissajous of the original signal sampled by 125 MSa/s; (b) the fourth power of the original signal; (c) phase error of the phase-locked state; (d) the constellation of the recovered IQ signal.
    BER versus received signal power for 2.5 Gbaud/5 Gbaud.
    • Table 1. Experimental Parameters

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      Table 1. Experimental Parameters

      ParameterSymbolValue
      Laser wavelengthλ1549.72 nm
      Received signal powerPs−45 to 35dBm
      Communication rateRb10 Gbps
      Linewidth (TX/RX)Δν300 Hz
      ResponsivityR0.85 A/W
      Power-splitting ratioK0.5
    • Table 2. Specification List about FPGA

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      Table 2. Specification List about FPGA

      NameParameter
      Fourth-power look-up tableInput bitwidth: 7 bitOutput bitwidth: 10 bit
      First-order active loop filterInput bitwidth: 10 bitOutput bitwidth: 32 bit
      Direct digital synthesizerPhase accumulator word: 32Output bitwidth: 16 bit
      Working clock125 MHz
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    Shaowen Lu, Yu Zhou, Funan Zhu, Jianfeng Sun, Yan Yang, Ren Zhu, Shengnan Hu, Xiaoxi Zhang, Xiaolei Zhu, Xia Hou, Weibiao Chen, "Digital-analog hybrid optical phase-lock loop for optical quadrature phase-shift keying," Chin. Opt. Lett. 18, 090602 (2020)

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    Paper Information

    Category: Fiber Optics and Optical Communications

    Received: Mar. 18, 2020

    Accepted: May. 25, 2020

    Published Online: Jul. 31, 2020

    The Author Email: Shaowen Lu (lushaowen@siom.ac.cn), Xia Hou (hou_xia@siom.ac.cn)

    DOI:10.3788/COL202018.090602

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