Semiconductor manufacturing is driven by the relentless demand for smaller, faster, and more efficient electronic devices, placing immense pressure on innovation and refinement. Optical proximity correction (OPC) stands as a cornerstone of computational lithography, addressing distortions and variations inherent in the photolithographic process. As technology nodes shrink, OPC’s role becomes increasingly critical in maintaining pattern fidelity, enhancing yield, and minimizing manufacturing defects. By correcting optical distortions that arise when printing fine features on semiconductor wafers, OPC ensures the accuracy and reliability of integrated circuit (IC) patterns. In this paper, we highlight the indispensable role of OPC in advancing semiconductor technology, emphasizing its contribution to the performance and scalability of next-generation electronic devices.

OPC has evolved from rule-based methods to sophisticated model-based approaches, leveraging advanced lithography simulations to optimize mask designs. These models accurately represent physical phenomena such as source shape, mask configuration, photoresist exposure, and development processes. Through iterative optimization, experimental data is used to calibrate these models, ensuring consistency between simulation and real-world results. This iterative process improves mask correction accuracy and adaptability, enabling the creation of high-resolution patterns. Researchers have meticulously optimized every aspect of the OPC process, from pattern selection to algorithm development, employing machine learning to accelerate and refine optimization strategies (Fig. 5). A pivotal area of advancement is the management and mitigation of line edge roughness (LER). LER, characterized by random fluctuations along the edges of lithographic patterns, becomes increasingly challenging as feature sizes shrink. Quantitative measurement techniques such as critical dimension scanning electron microscopy (CD-SEM) and atomic force microscopy (AFM), coupled with offline roughness evaluation tools, enable precise LER analysis. Power spectral density (PSD) analysis provides frequency-domain insights into parameters such as correlation length and roughness index, while stochastic modeling techniques, including Monte Carlo simulations and Gaussian models, enable the prediction of LER behavior under diverse process conditions. Transfer functions are critical for quantifying how LER propagates during the etching process, enabling predictions of final pattern characteristics based on initial measurements. Machine learning methods, such as neural networks and support vector machines (SVMs), analyze extensive datasets to optimize process parameters and predict LER effects. Probability prediction models play a vital role in estimating the likelihood of defects caused by LER. By leveraging statistical properties, these models calculate failure probabilities and inform the development of targeted mitigation strategies, thus enhancing yield and device reliability. These innovations enable effective LER management, directly enhancing semiconductor device performance. Design-technology co-optimization (DTCO) has advanced significantly, aligning design rules with the capabilities and constraints of cutting-edge lithography. By addressing manufacturing limitations during the design phase, DTCO improves both manufacturability and device performance. Recent developments in DTCO have proved highly effective in optimizing design rules and process conditions for advanced nodes, including 14 nm and 7 nm technologies. Techniques such as Monte Carlo simulations have been instrumental in analyzing the effects of various design parameters, resulting in improved design rules and reduced process variability. Model simulations play a critical role in DTCO by uncovering complex interactions between design rules and patterning technologies. This enables iterative refinements, enhanced patterning accuracy, and the application of customized optical proximity correction (OPC) and resolution enhancement techniques (RETs). Studies consistently highlight DTCO's ability to align design optimization with manufacturing capabilities, ensuring high manufacturability and yield. These developments collectively enhance the precision, reliability, and efficiency of lithographic processes, driving the ongoing trend toward device miniaturization and the creation of high-performance semiconductor devices.

OPC advancements have profoundly improved the precision and efficiency of photolithography, ensuring continued progress in semiconductor scaling. The integration of machine learning techniques, such as neural network-based OPC and graph convolutional network-based OPC, has revolutionized the field, delivering enhanced computational efficiency and prediction accuracy. In addition, understanding LER transfer functions and leveraging DTCO methodologies have strengthened pattern fidelity and expanded process windows. Looking ahead, OPC research will focus on refining optimization techniques and extending their applicability to even smaller technology nodes. As lithographic processes grow increasingly complex, more precise and robust OPC methods will be required. The integration of artificial intelligence and machine learning in OPC holds immense potential to automate and enhance the optimization process, paving the way for faster, more reliable solutions.