Fig. 1. (Color online) (a) Schematic structure of the silicon JNT. (b) Top-view SEM images of the silicon JNT after gate formation.

Fig. 2. (Color online) Drain current I_ds versus gate voltage V_g with V_ds = 10 mV at different temperatures (upper part) and corresponding transconductance g_m–V_g curves (lower part).

Fig. 3. (Color online) (a) Barrier height of the device channel is extracted by fitting the thermally activated current. The conduction band edge E_C reaches the Fermi level E_F at 2.40 V. Inset: transconductance g_m–V_g curves at low temperature. (b) Locally amplified transconductance g_m–V_g curves before gate voltage 2.40 V, which are successively shifted for clarify.

Fig. 4. (Color online) Arrhenius plots of the conductance G₁, G₂, G₃, and G₄ for each group. The inset: close-up of the curves around 75 K.

Fig. 5. (Color online) (a) The gate-voltage regulated transition temperature T_A and T_C. (b) The gate-voltage dependence of the density of state and the localization length.

Fig. 6. (Color online) The behaviour of electron hopping (a) from M-VRH to NNH in and (b) from ES-VRH to M-VRH in.