Laser & Optoelectronics Progress, Volume. 62, Issue 13, 1306016(2025)
FPGA-Based High-Speed Underwater Real-Time Laser Communication System
Fig. 4. ePIBMA architecture[29]. (a) PE processor; (b) ePIBMA block diagram; (c) eCSEE circuit
Fig. 7. BER and eye diagrams of the system using different equalizers. (a) Comparison of BER of different equalizers (inset: eye diagram of the system without equalizer); (b)‒(e) eye diagrams of the system with truncated zero-forcing pre-equalizer for N = 1, 2, 3, 4; (f)‒(i) eye diagrams of the system with original zero-forcing pre-equalizer for N = 1, 2, 3, 4
Fig. 8. System BER test with various RS encoding parameters. (a) Test flowchart; (b) comparison of BER
Fig. 10. RS decoder simulation. (a) Received data of decoder; (b) output data of decoder
Fig. 11. Underwater laser communication system based on FPGA. (a) Physical picture; (b) block diagrams of FPGA internal modules; (c) water tank
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Zhangxing Wang, Tao Wang, Shengjie Yu, Xiaoyu Shen, Renjiang Zhu, Lidan Jiang, Cunzhu Tong, Yanrong Song, Peng Zhang. FPGA-Based High-Speed Underwater Real-Time Laser Communication System[J]. Laser & Optoelectronics Progress, 2025, 62(13): 1306016
Category: Fiber Optics and Optical Communications
Received: Nov. 19, 2024
Accepted: Jan. 20, 2025
Published Online: Jul. 16, 2025
The Author Email: Tao Wang (wangt@cqnu.edu.cn), Peng Zhang (zhangpeng2010@cqnu.edu.cn)
CSTR:32186.14.LOP242279