[1] [1] BOZORG A, STASZEWSKI R B. A 002-45-GHz LN(T)A in 28-nm CMOS for 5G exploiting noise reduction and current reuse ［J］. IEEE J Sol State Circ, 2020, 56(2): 404-415.

[2] [2] JAFARNEJAD R, JANNESARI A, NABAVI A, et al. A low power low noise amplifier employing negative feedback and current reuse techniques ［J］. Microelec J, 2016, 49: 49-56.

[4] [4] GUO B, CHEN J, LI L, et al. A wideband noise-canceling CMOS LNA with enhanced linearity by using complementarynMOS and pMOS configurations ［J］. IEEE J Sol Sta Circ, 2017, 52(5): 1331-1344.

[5] [5] BIJARI A, ZANDIAN S, EBRAHIMIPOUR M. Optimum design of a new ultra-wideband LNA using heuristicmultiobjective optimization ［J］. J Comput Elec, 2020, 19: 1295-1312.

[6] [6] ZHANG H, FAN X, SINENCIO E S. A low-power, linearized, ultra-wideband LNA design technique ［J］. IEEE J Sol Sta Circ, 2009, 44(2): 320-330.

[7] [7] GOO J S, DONATI S, CHOI C H, et al. Impact of substrate resistance on drain current noise in MOSFETs ［M］. Springer Vienna, 2001: 182-185.

[8] [8] SABERKARI A, KAZEMI S, SHIRMOHAMMADLI V, et al.gm-boosted flat gain UWB low noise amplifier with active inductor-based input matching network ［J］. Integration, 2016, 52: 323-333.

[9] [9] DARYABARI F, ZAHEDI A, REZAEI A, et al. Gain-controlled noise-reduction LNA design using source-bulk resistors and double common-source topology ［J］. Integration, 2019, 68: 50-61.

[10] [10] DARYABARI F, ZAHEDI A, REZAEI A, et al. Low-power ultra-wideband LNA employing CS-CD current-reuse and gain-controller resistor technique in 018-μm CMOS technology ［J］. Analog Integr Circ & Signal Process, 2019, 101(2): 187-199.