Fig. 1. Architecture of readout circuit chip

Fig. 2. Architecture of configurable timing IP core

Fig. 3. Diagram of IP core internal connection relationship

Fig. 4. Diagram of configurable timing implementation method

Fig. 5. Simulation results of control timing. (a) Default timing; (b) timing after configuration modification

Fig. 6. Diagrams of row-column address switching. (a) Column address; (b) row address

Fig. 7. Simulation results of 32×32 window configuration

Fig. 8. Data transmission flowchart

Fig. 9. Diagrams of data bit-width conversion. (a) 21.0 MHz clock domain data schematic diagram; (b) 52.5 MHz clock domain data schematic diagram

Fig. 10. Simulation results of data processing circuit

Fig. 11. MPW test system. (a) Micrograph of MPW verification chip; (b) test platform for MPW chip

Fig. 12. Oscilloscope capture of control signal waveform

Fig. 13. Imaging results of filament under different integration times. (a) 5 ms; (b) 10 ms; (c) 20 ms; (d) 30 ms

Fig. 14. Imaging results of filament under different window configurations. (a) 40×20 window; (b) 30×40 window