The development of readout circuits is shifting towards large arrays, small pixels, and advanced processes to achieve flexible adjustment of operating states and array windowing. A customized digital module for a 2560 pixel×2048 pixel infrared focal plane readout circuit, based on 55 nm complementary metal-oxide-semiconductor (CMOS) transistor technology, is designed. This design incorporates a configurable timing intellectual property (IP) core using a state machine with unique thermal code encoding to regulate the control timing generation circuit. This enables configurable control timing for analog circuits while enabling array windowing. An asynchronous first input first output (FIFO) is employed for bit-width conversion and cross-clock processing of quantized data, ensuring accurate data transmission. Based on the same architecture and process, the verification chip design and multi project wafer fabrication with the window size reduced to 128 pixel×128 pixel are completed. The test results demonstrate the ability of the digital module to provide configurable control timing in specific readout circuit applications, ensuring quantized data accurate transmission.