Semiconductor Optoelectronics, Volume. 46, Issue 4, 673(2025)

Parallel Configurable FFE High-Speed SerDes Transmitter Design

REN Yifan, ZHANG Chunming, and TAO Baoming
Author Affiliations
  • School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, CHN
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    References(2)

    [1] [1] Wang J Q, Tan A, Iyer A, et al. 7.1 A 2.69 pJ/b 212 Gb/s DSP-based PAM-4 transceiver for optical direct-detect application in 5 nm FinFET[C]//2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, 67: 123-125.

    [2] [2] Kossel M A, Khatri V, Braendli M, et al. 8.3 An 8 b DAC-based SST TX using metal gate resistors with 1.4 pJ/b efficiency at 112 Gb/s PAM-4 and 8-Tap FFE in 7 nm CMOS[C]//2021 IEEE International Solid-State Circuits Conference (ISSCC), 2021, 64: 130-132.

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    REN Yifan, ZHANG Chunming, TAO Baoming. Parallel Configurable FFE High-Speed SerDes Transmitter Design[J]. Semiconductor Optoelectronics, 2025, 46(4): 673

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    Paper Information

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    Received: Apr. 15, 2025

    Accepted: Sep. 18, 2025

    Published Online: Sep. 18, 2025

    The Author Email:

    DOI:10.16818/j.issn1001-5868.20250415005

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