Owing to long transmission distances and high bit-error rates caused by serious channel attenuation, non-return-to-zero (NRZ) code signals are usually processed using forward feedback equalization (FFE) at high-speed serial interface (SerDes) transmitters. In this study, based on the UMC 28 nm CMOS process, a parallel-configurable FFE high-speed SerDes transmitter was designed using an 8-bit digital-to-analog converter architecture. The parallel input signal and stored 8 10-bit tap coefficients are logically operated by the multiplier module and parallel carry adder module in the configurable FFE to realize signal pre-equalization processing. A high-speed 4∶1 multiplexer composed of an AND-NOT gate, a cascode device, and a reset path was adopted. The terminal output network adopted a source series termination structure to reduce power loss. The simulation results showed that when the transmitter was powered by 1.05 V voltage and the channel attenuation was 18.59 dB @ 20 GHz, the eye height of the output 40 Gb/s NRZ signal was 378.4 mV, eye width was 18.53 ps (0.74 UI), overall layout area was 0.055 mm², overall circuit power consumption was 0.055 mm², and power consumption of the complete circuit was 41.8 mW.