Fig. 1. The proposed Si-SiN FOG chip and transceiver module. (a) Schematic illustration of the transceiver-based closed-loop FOG structure, consisting of the transceiver, signal detection circuit, as well as optical header. (b) One 8-inch Si-SiN photonics wafer comprising 1200 transceiver chips. (c) The packaged transceiver in a standard butterfly package. (d) One chip bar (1/4 reticle) comprising eight Si-SiN FOG chips with a Chinese 1 Yuan coin for scaling.

Fig. 2. The characterization of the chip. (a) The measurement and linear fitting of SiN waveguide loss using the cut-back method. (b) The measurement and linear fitting of the Si-SiN transition; the inset shows the simulated optical field. (c) The dark current and responsivity of the on-chip Ge PD; the inset shows the EO response of the PD. (d) The splitting ratio and loss test of the splitter using the imbalanced MZI method; the insets show the extinction ratio and the simulated optical field. (e) The chip-fiber edge coupler test result; the inset is the TE-polarized optical field from fiber to chip. (f) The measurement of the insertion loss and PER of the polarizer; the inset shows the simulated TE- and TM-polarized optical field.

Fig. 3. The characterization of the transceiver. (a) The spectrum of the transceiver with 100 mA driving current; the upper left inset shows the transceiver and a Chinese 1 Yuan coin for scaling, and the upper right inset shows the output power from nine positions covering the center and edge of the wafer. (b) Correlated function intensity of the spectrum; the upper right inset is the enlarged plot for better illustration.

Fig. 4. Transceiver-based FOG test. (a) IFOG output in 1 h. The inset is package pins indications and corresponding definitions. (b) Allan variance analysis results and fitting of the transceiver-based FOG and the on-shelf mature IFOG product.

Fig. 5. The 10 s bias stability comparison between different photonic-chip-based IFOGs. The relevant literature is highlighted with corresponding results. The data are either adapted directly from corresponding literature or calculated using the ARW values provided in the works where the value is not directly accessible.

Fig. 6. Representative full temperature (−45°C to 70°C) reliability test results. Full-temperature variation test results of the (a) output power and (b) PER.