Interferometric fiber optic gyroscopes (IFOGs) are widely employed in both military and civilian areas for their all-solid configuration with no moving parts, high reliability, high precision, and wide dynamic range [1–3]. With the fast development of miniaturized smart sensors, low-cost and small-sized FOGs are urgently demanded. In recent years, photonic integrated circuits (PICs) and miniaturized PIC-based FOGs have been intensively researched [4–20]. For example, in 2019, by integrating the passive fiber couplers and polarizers on a low-loss SiN photonic chip, KVH Co. demonstrated an open-loop FOG with the bias instability of 0.048 deg/h [7]. In 2022, Shang et al. replaced the passive fiber coupler with a planar lightwave circuit (PLC)-based Y branch chip. The discrete super-luminescent diode (SLD) optical source and photodetector (PD) are hybridly packaged using the edge coupling scheme with high alignment precision, with the help of small-sized electronic chips and fiber coils. The miniaturized FOG shows bias stability of ∼0.18 deg/h at an integration time of 10 s [12]. Based on a similar method, Suo et al. demonstrated an IFOG with ultra-small diameter polarization maintaining (PM) photonic crystal fiber coils, of which the 10 s bias stability is ∼0.16 deg/h [13]. In 2023, Guo et al. proposed a three-axis passive integrated coupler chip based on the PLC process. By optimizing the chip loss and avoiding the on-chip optical crosstalk, all the three axes showed bias stability of ∼0.045 deg/h at an integration time of 10 s, which is comparable to traditional FOGs [16]. In 2023, Wang et al. proposed a silicon photonic chip where the modulator, PD, and other passive devices are integrated. Since the traditional bulk lithium niobate multifunctional integrated optical chip (MIOC) is avoided, the size is significantly decreased, and the bias stability is ∼1.8 deg/h at an integration time of 10 s [17]. The aforementioned schemes have laid solid foundations for the miniaturized FOGs, however, there are still several issues that need to be addressed. First, low-loss SiN [7,14] and PLC chips [12,13] are indeed suitable for replacing discrete passive fiber devices, however, the practical on-chip modulation and photodetection scheme are still less explored, which limits these two kinds of chips from further integration. Second, simultaneously aligning the SLD chip source and photodetector with high precision is difficult for large volume production with high efficiency. In addition, based on the proton-exchange processing principle, PLC chips lack the capability of further miniaturization because of the smaller index difference between the core and cladding materials. Third, since the silicon waveguide still features high waveguide loss (∼2dB/cm), weak-linearity modulators, the reported FOG based on silicon photonic chip has not met the application criteria. Furthermore, the use of grating couplers [17] also suffers from low bandwidth and high reflection [21], which may degrade the precision.

To address these concerns, in this work, we have proposed compact Si-SiN photonic FOG transceivers based on typical CMOS compatible silicon photonic platforms [22–25]. In our scheme, the PDs are integrated on-chip using the mature germanium (Ge) epitaxy process [26,27]. The use of the SiN layer simultaneously guarantees low propagation loss and permits direct coupling with PM fibers (∼6μm MFD) used in FOGs. Small mode field diameter (MFD) fibers (∼3μm) and MFD transition fibers (3 μm to 6 μm) used in pure silicon photonics are therefore circumvented, which greatly enhances the coupling efficiency. The Si-SiN chip is assembled in a standard butterfly package (22mm×12.6mm×8.1mm) with a small-sized SLD chip. The total insertion loss is estimated to be ∼6.98dB and the polarization extinction ratio (PER) is larger than 20 dB at room temperature. To maintain high performance, the carrier-dispersion-based silicon modulators have not been integrated because of the weak linearity and imbalanced loss induced by the voltage-dependent transmission loss. The transceiver-based FOG test has shown record-low 0.022 deg/h bias stability at an integration time of 10 s and 0.0012deg⁡/h angular random walk (ARW) among all photonic-chip-based FOG systems, which is comparable to the on-shelf mature product. Our work provides a promising FOG transceivers solution with large volume manufacturing and low-cost capability, which may promote a high-performance, low-cost, and miniaturized IFOG system.

Traditionally, the high-polarization FOG optical transceiver module is composed of an SLD optical source, a PM fiber splitter, and a PD, which are well packaged separately and connected by PM fiber splicing at three points (SLD–splitter, splitter–PD, splitter–MIOC) [1,2]. The discrete device and assembling cost take a large portion of an FOG system. As one of the most important platforms for integrated photonics, silicon photonics is known for natural CMOS compatibility (low cost and mature processing techniques), ultra-small chip size (high refractive index difference between silicon core and silica cladding), as well as complete designing tools for various on-chip functional active and passive devices.

Figure 1 shows the proposed Si-SiN photonic FOG chip and transceiver module. As shown in Fig. 1(a), the PM splitter, on-chip Ge PD, and polarizer are directly integrated on the Si-SiN chip and are optically connected by a low-loss SiN waveguide. By integrating the photonic chip with an SLD chip into the standard butterfly package with a thermo-electric cooler (TEC), the transceiver shares the same size as the traditional SLD module, as shown in Fig. 1(c), where the output fiber could be directly PM spliced with the input fiber of the MIOC and form the complete optical transceiver part of the FOG system. No other fiber splicing work is needed, such that the splicing points are decreased by 66%. Our transceiver chip is fabricated on an 8-inch (200 mm diameter) silicon photonics wafer (43 complete reticles) based on CUMEC’s leading 130 nm Si-SiN photonics platform [28,29], as shown in Fig. 1(b), where the thicknesses of buried oxide (BOX) and SiN are 3 μm and 300 nm, respectively. The gap between the Si and SiN is 230 nm. The size of the chip is 5mm×2.3mm. Figure 1(c) shows a chip bar (1/4 of one reticle size) comprising eight transceiver chips, and a Chinese 1 Yuan coin is demonstrated for scaling. It is noteworthy that a single 8-inch wafer could yield ∼1200 transceiver chips, which is very suitable for small-size and low-cost miniaturized FOG production.

The use of the SiN layer is twofold. First, benefitting from the excellent passive performance, the edge couplers (ECs), on-chip polarizers, PM splitters, and waveguides are patterned in this layer. Second, the MFD of the MIOC is ∼6μm for the 1310 nm band, which does not match with the narrowest 130 nm width silicon waveguide (∼3μm), while the ∼190nm width SiN waveguide is enough for MFD matching and direct coupling. The use of the Si layer permits on-chip PD formation using the mature Ge epitaxy process [26]. The combination of these two layers ensures high-performance passive and active on-chip devices.

Figure 2 shows the characterizations of the on-chip components using on-chip grating couplers as the input and output. The cut-back method is used to evaluate the transmission loss of the SiN waveguide, as shown in Fig. 2(a). The linear fitting suggests the loss of 0.31 dB/cm at 1310 nm, which is much lower than that in the single-mode silicon waveguide (∼2dB/cm). Note that in recent literature, the SiN waveguide propagation loss is significantly reduced to ∼0.05dB/cm or less [30–32], where the dielectric SiN film is grown using the low-pressure chemical vapor deposition (LPCVD) process with ultra-high temperature (>1000°C) for reducing absorption loss [30,33], which will degrade the functionality of the active Ge PD device pre-fabricated in former steps. Therefore, in our scheme, the temperature-friendly (<400°C) plasma-enhanced chemical vapor deposition (PECVD) process is utilized [34], which simultaneously enables high-performance on-chip PDs and moderate transmission loss. Figure 2(b) shows that the extracted Si-SiN vertical coupler loss is 0.14 dB, which ensures low-loss vertical coupling between the two dielectric layers; the inset is the simulated TE-polarized optical field at 1310 nm. Dark current and responsivity are important for detection precision and signal-to-noise ratio (SNR) of the FOG. In our test, the on-chip Ge PD demonstrates ∼5.5nA dark current and ∼0.99A/W responsivity (∼93.7% quantum efficiency), which are comparable to the traditional discrete InGaAs PD, as shown in Fig. 2(c). The inset of Fig. 2(c) shows the electro-optical (EO) response of the PD, indicating the 3 dB bandwidth of 18.5 GHz, which ensures ultra-high-speed operation. To both decrease the back-reflection and eliminate the undesired power in higher-order mode widely existing in a 2×1 splitter, a 2×2 splitter is employed in our scheme. Optionally, a monitor PD could be easily integrated for power monitoring and stabilizing for this configuration, as shown in Fig. 1(a). The imbalanced Mach–Zehnder interferometer (IMZI) scheme is applied to precisely evaluate both the splitting ratio and loss of the splitter [35]. The extinction ratio is ∼32dB at 1310nm±30nm, which corresponds to the splitting ratio of 51.2:48.8. The extracted insertion loss is 0.15 dB, as shown in Fig. 2(d), where the lower inset shows the simulated TE-polarized optical field.

The edge coupler is preferred in our scheme for three reasons. First, it is easy to realize broad bandwidth operation [21]. Second, simply tilting the output waveguide could effectively avoid the back-reflection, which has been widely adopted in the MIOC chip [1,2]. Third, it is convenient for packaging and adapts to the existing FOG system. As shown in Fig. 2(e), the chip–fiber coupling loss is ∼2.3dB over 100 nm bandwidth. Such wideband operation ensures smooth spectrum envelope with small ripple [Fig. 3(a)], which is critical for reaching high detection precision. Compared with the PLC-chip-based scheme, our chip is naturally suitable for a high-polarization FOG system, which is immune to the polarization crosstalk widely existing in the low-polarization system. The on-chip polarizer is designed using the phase-matching principle [36], where TM-polarized light satisfying the phase-matching condition is filtered from the neighboring waveguide and then absorbed using the doping silicon waveguide [37] by low-loss vertical couplers, while TE-polarized light is transmitted through the main waveguide. The simulated optical field is shown as the inset of Fig. 2(f), where the loss and PER are 0.35 dB and 26.9 dB, respectively.

The transceiver chip is packaged with a TEC and an SLD chip in a standard butterfly package. The SLD, PD, and TEC are wire bonded to the package pins with inter-spacing of 1.27 mm. Figure 3 shows the characterizations of the packaged FOG transceiver at 100 mA driving current. The optical spectrum presented in Fig. 3(a) shows that the spectral ripple is 0.11 dB and the 3 dB bandwidth is 30.5 nm, which are consistent with the SLD chip measurement, meaning that the chip-induced dispersive back-reflection or loss is negligible. The upper left inset shows the actual packaged transceiver with a Chinese 1 Yuan coin for scaling. Figure 3(b) shows the correlated function intensity of the spectrum by applying fast Fourier transform (FFT) operation [1]. The enlarged plot of the inset indicates that the second peak value is below -64 dB, which is clean enough for FOG application. Table 1 summarizes the parameters of the transceiver. The output power is 1127.2 μW (0.52 dBm) under 100 mA driving current. Note that the SLD chip power is ∼7.5dBm with ∼13dB PER, and therefore, the insertion loss of the chip is 6.98 dB. According to previous measurements shown in Fig. 2, the SLD–chip coupling loss is calculated as ∼1.18dB, which is the highest coupling efficiency among all reported results, to the best of our knowledge. The upper right inset of Fig. 3 shows the output power from nine positions covering the center and edge of the wafer. Although suffering from polishing and manual coupling deviations, all the output power exceeds 1 mW, indicating that most of the chips on the wafer support the high-performance transceiver. In the future, the utilization of an automatic coupling platform being built will alleviate such power deviation. Note that the PER of 25.8 dB is not consistent with the polarizer test result shown in Fig. 2(f), which is attributed to the stress-induced moisture-forbidden adjoint for further reliability test.Table 1.

Main Parameters of the FOG Transceiver

The transceiver is a PM fiber spliced with the MIOC. The PD output signal is connected to the FET located on the signal processing circuit using common flying wires. All the other driving and signal wires are connected according to the package pins definition shown as the inset of Fig. 4(a). The driving current of the SLD is 120 mA, and the average diameter and length of the fiber coil are 70 mm and 580 m, respectively. Figure 4(a) presents closed-loop FOG system test results in 1 h, where the sampling rate is 1 Hz and the average output is 7.7 deg/h, which is nearly consistent with the horizontal component of Earth rotation rate of ∼7.4 deg/h in Chongqing city. Figure 4(b) is the Allan variance analysis of the IFOG output value, where bias stability is 0.022 at 10 s integration time, the ARW is 0.0012deg⁡/h, and the bias instability reaches 0.003 deg/h. These test results are record-low compared with other photonic-chip-based FOGs, as shown in Fig. 5, where the bias stability at an integration time of 10 s is marked. Three possible reasons are extracted for the improvement. First, compared with the PLC-chip-based scheme, our chip is highly-polarized, which is helpful to decrease the polarization crosstalk that widely exists in the low-polarization system. Second, since the output light is highly-polarized, the halfly-power loss is avoided when passing through the MIOC. Together with high coupling efficiency from the SLD light source, the SNR of the signal carrying Sagnac phase information is higher (over 50 μW power injected into the PD). Third, since the Ge PD is waveguide-coupled in the buried oxide cladding layer, only the signal light carrying Sagnac phase information transmitted inside the waveguide could be effectively detected. The stray light not fulfilling the single-mode condition is scattered outside the PD area (such as the dummy area of the Si or SiN layer).

As a comparison, the Allan variance analysis of the on-shelf mature IFOG product with the same fiber coil is also presented in Fig. 4(b). The bias stability at 10 s integration time is 23% superior to the transceiver-based FOG. This is mainly caused by the long flying wires (approximately tens of centimeters) between the PD and FET located on the signal processing circuit, which will induce significant environmental noise and worsen the analog electric signal. Furthermore, the processing circuit is also not optimized to fully adapt to the transceiver. These will be the focus for the next step.

To fulfil the stringent conditions for the FOG product, we evaluate the transceivers by measuring full-temperature (FT, −45°C to 70°C) power and PER of the output light using different packaging schemes. After conducting lots of necessary reliability experiments, the full-loop packaging scheme is near to be settled. Figure 6 shows one of the most recent representative FT power and PER variation test results. The FT power change [100×(Pmax−Pmin)/(Pmax+Pmin)] is below 3%, which is better than that of the discretely packaged SLD source. The FT PER is greater than 20 dB. The maximum and minimum PERs are 27.58 dB (TE light power: 1125.2 μW) and 22.36 dB (TE light power: 1120.7 μW), respectively, only 4.5 μW FT power variation for a transceiver with 1127.2 μW output power.

On one hand, three-axis FOGs requiring three PDs are desired for the inertial measurement system (IMU). However, for passively integrated PLC [16] or SiN platforms where the PDs are placed externally, the extra precision aligning work significantly increases the coupling difficulties, manufacturing efficiency, as well as the packaging costs. Furthermore, when inducing the output waveguides to the external PDs, on-chip optical inter-crossings may be inevitable. The resulting signal crosstalk will degrade the measurement reliability and accuracy. Fortunately, the Si-SiN platform supporting on-chip PDs is suitable for multiaxis extension by simply tripling the current design with an on-chip 1×3 power splitter. The packaging flow, reliability evaluation, as well as the size remain the same as the single-axis photonic chip. The three-axis transceiver is being fabricated using the same platform, and on-chip electrical crosstalk between PDs will be the key step before the FOG system test. On the other hand, to further enhance the FOG stability and signal quality, implementation of a monitor PD (MPD, see Fig. 1(a) for reference) for feedback controlling the SLD output power and balanced PDs (BPDs) for removing the environmental noise has been proved effective in a high-speed coherent optical communication system [38]. It is feasible to realize the MPD and BPD by simply placing PDs with an appropriate passive device, such as on-chip non-symmetrical directional couplers and phase delay structures.

Recent studies have shown that an on-chip sensing coil is possible in virtue of the ultra-thin SiN waveguide technique [39–41] featuring sub-0.2 dB/m transmission loss. Moreover, silicon photonics with heterogeneously integrated thin-film lithium niobate (TFLN) have also achieved remarkable progress in recent years [42]. The above progress has made on-chip high-linearity modulators and sensing coils possible. Together with the presented transceiver integrating other high-performance optical functions, we believe our devices lay solid foundations for future all-optical gyroscopes [5,39], which will greatly optimize the fabrication process, the size, and the cost of next-generation FOGs for large-scale deployment and application scenarios.

In summary, a kind of highly polarized FOG transceiver fabricated on a typical CMOS-compatible 8-inch Si-SiN photonic platform is presented. Combined with high-performance passive and active devices of SiN and Si layers, the chip features low insertion loss, high output power and PER. Built with a fiber coil with 70 mm diameter and 580 m length, the transceiver-based IFOG exhibits record-low bias stability of 0.022 deg/h at an integration time of 10 s, the ARW of 0.0012deg⁡/h, and the bias instability of 0.003 deg/h compared with the previous reports based on photonic chips. The reliability tests are nearly completed for potential mass application requirements in the near future. Our work provides a promising solution toward both single- and three-axis on-chip FOG systems with large volume manufacturing capability.

Acknowledgment. We gratefully acknowledge the Technology Development Center and Process Manufacturing Center of CUMEC for process development and device fabrication. We gratefully thank the Packaging & Test group of the Silicon Photonics Center of CUMEC for chip characterization and packaging.