Journal of Semiconductors, Volume. 46, Issue 7, 070204(2025)

High-precision ADC design techniques in ISSCC 2025

Bingrui Li1,2, Zongnan Wang1,2, and Xiyuan Tang1,2、*
Author Affiliations
  • 1Institute for Artificial Intelligence, Peking University, Beijing 100871, China
  • 2School of Integrated Circuits, Peking University, Beijing 100871, China
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    ADCs are not standalone blocks—their peripheral circuits, together with the ADC core, have a significant impact on system-level performance. ISSCC 2025 showcased some pioneering co-design architecture that optimize ADC cores alongside peripheral circuits including input buffers and filters. In Ref. [8], Luan et al. focused on the input stage and proposed a gain-embedded bootstrapped sampler, as shown in Fig. 3(a). The sampler is a PMOS transistor whose gate and drain are connected to the feedback signal through two CDACs. The input signal connects to the source, making the transistor work as a Gm cell. Since the sampler only draws a small current that relates to the residue signal, the driving requirements are relaxed. In addition, this structure also features lower sampling noise, good linearity and weaker kickback. In Ref. [9], Ye et al. proposed a continuous-time correlated level shifting (CLS) technique that realized a rail-to-rail high-linearity input buffer, as shown in Fig. 3(b). An extra CLS capacitor and level shift phase are added compared to conventional CLS[10]. After sampling the coarse version of input, the two CLS capacitors are connected in series at the output of the amplifier one by one. Therefore, the output swing can be extended and the equivalent open-loop gain can be boosted at the end of the second level shift phase, leading to a rail-to-rail linear operation. In Ref. [6], Chen et al. also put efforts into the innovation of the input buffer and proposed a split coarse-fine input-buffer-sampling scheme, as illustrated in Fig. 3(c). The input buffer is split into a low-power push−pull source follower as the coarse buffer and a high-power cascoded one as the fine buffer. During sampling, the coarse buffer first charges its loading capacitor CS,C to a value close to the input signal, and then, the input directly connects to CS,C, resulting in a small differential voltage to the fine buffer. Finally, a coarse ADC quantizes and injects the results to CS,C, generating the required residue signal. Since the fine buffer always processes a small input during the whole period, high linearity can be ensured. Beyond buffer optimization, filter-ADC co-design was also discussed in ISSCC 2025. In order to relax the base-band filter requirements before the ADC as well as maintain a wide bandwidth and high efficiency, Huang et al. proposed a filter-embedded pipelined-SAR architecture, as depicted in Fig. 3(d)[2]. By incorporating an 8-tap FIR filter cascaded by a 3rd-order IIR filter into the CDAC, the ADC achieves anti-aliasing characteristics with better efficiency and smaller area. In contrast to conventional filter-embedded SAR ADCs[11], the proposed ADC mitigates the speed penalty of the filtering operation through progressive conversion.

    (Color online) The ADC and peripheral circuits co-design techniques. (a)−(c) ADC-buffer co-design techniques[6, 8, 9]; (d) ADC-filter co-design techniques[2].

    Figure 3.(Color online) The ADC and peripheral circuits co-design techniques. (a)−(c) ADC-buffer co-design techniques[6, 8, 9]; (d) ADC-filter co-design techniques[2].

    High-precision analog-to-digital converters (ADCs) serve as fundamental components in modern electronic systems, bridging physical analog world and digital intelligence. They find ubiquitous applications across diverse domains, ranging from internet of things (IoT) to embodied artificial intelligence systems. Achieving high precision necessitates various circuit techniques including high-performance amplifiers and advanced calibration schemes. Furthermore, the evolution of ADC architectures has gradually elevated the significance of peripheral circuitry co-design in optimizing system-level performance metrics. In ISSCC 2025, several techniques are proposed to address these challenges.

    Amplifiers are typically the main bottleneck in the performance and efficiency of high-precision ADCs. The open-loop charge-transfer amplifier is a promising candidate for its good efficiency. However, conventional ones suffer from poor power supply rejection ratio (PSRR) and common-mode rejection, leading to the signal-to-noise ratio (SNR) and robustness challenge[1]. To overcome these problems, Huang et al. proposed a floating charge transfer topology, where the transistors are powered by a floating capacitor as shown in Fig. 1[2]. As input and output currents of the capacitor are forced to be equal, supply noise will be forced to circulate within the amplifier. The post-layout simulation shows that the gain variation is limited to ±2.7% over process-voltage-temperature (PVT) variations without any trimming.

    In summary, the designs presented in ISSCC 2025 exhibit several notable trends: 1) The performance metrics are gradually approaching the theoretical limits. Fig. 4 illustrates the positions of the works this year among all published works in ISSCC and VLSI. The performance boundaries are further extended, e.g., Ref. [3] achieves the best FoMs to date. Table 1 shows the detailed performance summary. It must be emphasized that while competitive FoM remains a notable criterion for quality designs, it is neither the sole nor the most critical standard. Important metrics such as input swing and area—often decisive factors in application-specific scenarios—are not captured in FoM calculations. 2) Design improvements are increasingly focused on system-level optimization, including refinements of ADC architecture and calibration techniques. Transistor-level innovation targeting at individual sub-blocks only accounts for a small portion. Therefore, in circuit design, it is important to go beyond individual transistor analysis and adopt a more systematic approach. 3) Designers are expanding their horizons beyond the ADC core itself. Many works pay attention to the peripheral circuits including filters and input buffers. Thus, exploring the techniques which can ease system integration is an increasingly important direction for future advancement.

    (Color online) The survey of (a) energy over SNDR and (b) FoMs over bandwidth[12].

    Figure 4.(Color online) The survey of (a) energy over SNDR and (b) FoMs over bandwidth[12].

    (Color online) The DEM[3, 4] ((a) and (b)) and calibration ((c) and (d)) techniques[5, 6].

    Figure 2.(Color online) The DEM[3, 4] ((a) and (b)) and calibration ((c) and (d)) techniques[5, 6].

    (Color online) The high-performance amplifier techniques[2].

    Figure 1.(Color online) The high-performance amplifier techniques[2].

    Fabrication-induced variations, such as inter-stage gain errors and capacitor mismatches, can degrade ADC performance. Researches presented several improvements in dynamic element matching (DEM) and calibration techniques this year to address these challenges. Zhao et al. implemented a 120 dB signal-to-noise-and-distortion ratio (SNDR) 189 dB Schreier figure-of-merit (FoMs) noise-shaping (NS) successive approximation register (SAR) ADC with hybrid mismatch shaping and system-level chopping as shown in Fig. 2(a)[3]. The 8b capacitor digital-to-analog converter (CDAC) is segmented into 3 most significant bits (MSBs) with 8 equal capacitors and 5 binary-weighted least significant bits (LSBs). Data weighted averaging (DWA) and mismatch error shaping (MES) are applied to the MSBs and LSBs respectively, increasing the quantizer resolution effectively. System-level chopping is adopted to eliminate the offset, 1/f noise, and the VCM induced CDAC nonlinearity simultaneously. In Ref. [4], Gao et al. extended the MES to multi-stage applications and presented a 93.3 dB-SNDR 180.4 dB-FoMs calibration-free NS pipelined-SAR ADC with cross-stage gain-mismatch-error-shaping technique as depicted in Fig. 2(b). An extra capacitor CFB is added in the 1st-stage CDAC to serve as the mismatch reference of the 2nd-stage CDAC and residue amplifier. By involving CFB in the MES procedure of the 1st stage, both the capacitor mismatch of two stages and the gain error can be shaped and eliminated. This work further solved the MES saturation problem by pre-comparison during sampling. Sampling noise is a critical problem for discrete-time (DT) ADCs. Wang et al. proposed a single-amplification-based kT/C noise cancellation technique, and implemented a 92.5dB-SNDR 184.8dB-FoMs incremental NS pipeline ADC with a dither-based background gain error calibration scheme as shown in Fig. 2(c)[5]. In the design, single amplifier is used for the multi-cycle kT/C noise-cancelled conversion. This is enabled by moving the noise-cancellation amplifier out of the noise-shaping loop and utilizing dual CNC in a ping-pong fashion. By injecting dither in both sampling and residue amplification phases, the calibration engine can expand the kT/C noise-limited SNR beyond 100 dB with only 0.8 pF sampling capacitance. Another technique to solve the gain error problem is proposed in Ref. [6]. Chen et al. exploited the metastability and proposed a fast and robust background calibration technique in a 79.4dB-SNDR 176.3dB-FoMs pipelined-SAR ADC, as shown in Fig. 2(d). This work adopts an improved version of the opportunistic PN-injection-based calibration[7]. By monitoring the probability of metastability and adjusting the comparator delay, the metastability can be better controlled, leading to fast and robust calibration without affecting ADC’s normal conversion. In addition, the offset is cancelled by equalizing the likelihood of the second-stage MSB resolving to 1 or 0.

    • Table 1. Performance summary of high-precision ADCs in ISSCC 2025.

      Table 1. Performance summary of high-precision ADCs in ISSCC 2025.

      ParametersZhao et al.[3]Luan et al.[8]Gao et al.[4]Wang et al.[5]Ye et al.[9]Chen et al.[6]Huang et al.[2]
      1Conversion rate/filter sampling rate, 2without input buffer/with input buffer, 3FoMS=SNDR+10log10(BW/Power).
      ArchitectureNS-SARPPD ZOOMNS pipelined-SARIncremental NS pipelineNS-SARPipelined-SARFilter-embedded pipelined-SAR
      Process (nm)180555528552228
      Area (mm2)0.150.0290.0280.0340.0430.060.036
      Supply (V)1.8/51/1.21.20.91.21.8/0.9
      Fs (MHz)2.048120164016350/28001
      BW (kHz)14156.258002500800080 000
      Power (μW)139.112.2307467.3470/11502450/162024870
      SNDR (dB)120.699.693.392.582.979.470.1
      SFDR (dB)132.5112.8112.2105.499.483.4
      DR (dB)123.510295.0293.183.281.872
      FoMs3 (dB)189.2184.8180.4184.8180.2/176.32181.9/176.32172.2

    [1] N Dolev, M Kramer, B Murmann. A 12-bit, 200-MS/s, 11.5-mW pipeline ADC using a pulsed bucket brigade front-end, C98(2013).

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    Bingrui Li, Zongnan Wang, Xiyuan Tang. High-precision ADC design techniques in ISSCC 2025[J]. Journal of Semiconductors, 2025, 46(7): 070204

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    Paper Information

    Category: Research Articles

    Received: May. 9, 2025

    Accepted: --

    Published Online: Aug. 27, 2025

    The Author Email: Xiyuan Tang (XYTang)

    DOI:10.1088/1674-4926/25050012

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