Fig. 1. Block diagram of hardware design for lidar acquisition and storage system

Fig. 2. Block diagram of FPGA logic design

Fig. 3. Design of ADC acquisition circuit

Fig. 4. High speed synchronous trigger circuit

Fig. 5. Multichannel data cache

Fig. 6. TDC algorithm based on multilevel IODELAY

Fig. 7. Schematic of delay time comparison

Fig. 8. Schematic of test system

Fig. 9. Test waveform of system

Fig. 10. ADC sampling spectrum

Fig. 11. Test system of high bandwidth acquisition storage

Fig. 12. Test of high bandwidth transmission verification