Fig. 1. Schemes of (a) existing DNNs and (b) the proposed chip.

Fig. 2. Simulation classification for the designed chip. (a) Input digits. (b) Simulation results. (c) Intensity distributions.

Fig. 3. Schemes of the experimental setup and fabricated chip. (a) Schematic diagram of the experimental setup. (b) Photo of the experimental setup. (c) The fabricated chip. (d) Partial enlarged view of the chip.

Fig. 4. Experimental classification for the designed chip. (a) Input digits. (b) Experimental results. (c) Intensity distributions.

Fig. 5. Cycle-test intensity results. (a) Intensity distribution of digit “1”. (b) Intensity distribution of digit “8”. (c) Intensity distribution of digit “9.”

Fig. 6. Cycle-test consistency results. (a1) Simulation and (a2) experimental confusion matrices. (b) Accuracy of the 10-cycle test. (c) Consistency of the 10-cycle test.

Fig. 7. Fabrication steps for the three-layer chip.

Fig. 8. Handwritten digit “0 to 4” classification for a three-layer chip. (a) Input digits. (b) Simulation results. (c) Experimental results. (d) Intensity distributions.

Fig. 9. Handwritten digit “5 to 9” classification for a three-layer chip. (a) Input digits. (b) Simulation results. (c) Experimental results. (d) Intensity distributions.

Fig. 10. Simulation classification accuracy for different numbers of layers for 10,000 test targets in the MNIST test data set.

Fig. 11. 3D microscope characterization of the step thickness of the proposed diffractive neural networks.

Fig. 12. Amplitude-encoded experimental fabricated targets.