Fig. 1. Conceptual diagram and structural schematic of the AON-D2NN. (a) The conceptual diagram of AON-D2NN. Multiple cores introduced by different wavelength channels in the chip can process multiple classification tasks in parallel. (b) The structural schematic of the AON-D2NN. The input data are encoded and loaded onto the input waveguide array using thermal phase shifters. Light of different wavelengths is simultaneously injected into the diffractive slab waveguide, enabling parallel processing. At the output port, the inference results for each task are determined based on the magnitude of the light intensity, allowing for concurrent task execution.

Fig. 2. Fabrication and characterization of AON-D2NN chip. (a) The microscope photograph of the fabricated chip. (b) The photograph of the packaged chip. It consists of an input layer, three hidden layers, and an output layer. The input layer is constituted by a set of 64 waveguides, each equipped with a thermal phase shifter that facilitates phase encoding. The hidden layers are composed of a diffractive slab waveguide covered by an array of phase shifters and germanium materials, which serve to implement linear matrix operations and nonlinear activation functions, respectively. The output layer is composed of ten output waveguides. (c) The measured output optical power varies with the applied power of a single electrode. (d) Measured response curve of the AON-D2NN. The x-axis represents the optical power entering the photonic chip, which is obtained by subtracting the coupling loss of the grating from the laser output power. The y-axis denotes the normalized total optical power measured at all output ports of the chip. (e) Schematic structure of the test activation function. A germanium block with dimensions of 2.8μm in length, 0.5μm in width, and 0.26μm in height is placed on a waveguide with a width of 0.7μm and a height of 0.22μm. (f) Measured response curve and the simulated optical propagation fields of the test activation function.

Fig. 3. Experiment results of AON-D2NN chip, compared with the linear configuration. (a) Conceptual diagram illustrating the role of nonlinearity in neural networks. (b) The cost function of the training datasets and the test datasets of the binary classification task. (c) The accuracy of the training datasets and the test datasets of the quadruple classification task with and without activation function. (d) Confusion matrix of the quadruple classification task after training without activation function. (e) Confusion matrix of the quadruple classification task after training with an activation function. (f) The inference results of some data samples.

Fig. 4. Experiment result of the multi-task learning. (a) The experiment result of the cross-training with the number of iterations. (b) The confusion matrix of the two tasks during the iteration.

Fig. 5. Experiment results of the AON-D2NN chip with multi-thread processing. (a) The specific experimental setup of multi-thread processing. (b) Comparison of the results obtained from two binary classification inference tasks under two-thread parallel processing and sequential task processing. Task 1 involves distinguishing between the digits “0,” “5” and “1,” “8,” whereas task 2 distinguishes between “0,” “1” and “5,” “8.” (c) The inference results of some data samples.