Semiconductor Optoelectronics, Volume. 46, Issue 3, 409(2025)

UIS Characteristics of A 4H-SiC Superjunction UMOSFET

CAO Rong and FENG Quanyuan
Author Affiliations
  • Institute of Microelectronics, Southwest Jiaotong University, Chengdu 611756, CHN
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    This study focuses on designing and optimizing a 4H-SiC superjunction trench field-effect transistor structure (DP-SJ-UMOS) with two segments of different P-pillar concentrations. The device′s UIS testing circuit was analyzed and its fundamental operating principles determined. The UIS characteristics of this device structure were studied in detail using Sentaurus TCAD simulation software, where three methods were proposed to improve avalanche tolerance. Multiple epitaxial growth and high-energy ion-implantation techniques were employed in the drift region to form the upper and lower segments of the superjunction structure with different concentrations, enhancing the avalanche current path during avalanche breakdown. This modification reduced the current of the parasitic transistor during breakdown, effectively suppressing the activation of the parasitic transistor and improving avalanche tolerance. The experimental simulations indicate that the proposed structure, compared with conventional superjunction devices (Con-SJ-UMOS), achieves a 1.5% increase in peak current, with breakdown voltage and avalanche tolerance enhancements of 24.5% and a 0.9%, respectively.

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    CAO Rong, FENG Quanyuan. UIS Characteristics of A 4H-SiC Superjunction UMOSFET[J]. Semiconductor Optoelectronics, 2025, 46(3): 409

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    Paper Information

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    Received: Aug. 12, 2024

    Accepted: Sep. 18, 2025

    Published Online: Sep. 18, 2025

    The Author Email:

    DOI:10.16818/j.issn1001-5868.20240812003

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