Fig. 1. Schematic diagram of failure analysis system prototype architecture

Fig. 2. Design scheme of the Event Time

Fig. 3. Framework of EPICS generalTime

Fig. 4. Judgment logic of the Event Time status

Fig. 5. Logic diagram of the Event Time internal status

Fig. 6. Screen capture of the unsynchronized (a) and synchronized (b) signals between 500 MHz vs. 10 MHz

Fig. 7. Block diagram of the timestamp accuracy measurement

Fig. 8. Measurement of the PPS signal jitter

Fig. 9. Block diagram of the data acquisition experiment

Fig. 10. Design of the structure data

Fig. 11. Structure data from different test stations of the experiment

Fig. 12. Data collection and analysis of simulated failure event