Fig. 1. (a) Definition of inverted chip assembly; (b) inverted chip assembly on various substrates^[32]

Fig. 2. Schematic process flow for (a) direct (O₂ plasma-assisted/SiO₂ covalent) wafer bonding and (b) intermediate layer wafer bonding (DVS-BCB)^[41]

Fig. 3. Illustration of area magnification in transfer printing III-V coupons from the III-V source substrate to the SOI target substrate. (a) Patterned stamp; (b) two source substrates with patterned coupons, (c) SOI target substrate^[51]

Fig. 4. Process flow of micro-transfer printing. (a) InP starting layer stack; (b) coupon patterning; (c) tether definition and release etch; (d) top view; (e) pick-up of the coupon from the source substrate; (f) printing of the III-V coupon to the SOI target substrate^[51]

Fig. 5. Overview of heterogeneous epitaxial integration of mismatched materials for photonic devices^[67]

Fig. 6. (a) 3D schematic of the ICL heterogeneously integrated with a silicon waveguide; (b) cross-sectional schematic of the hybrid III-V/Si active region; (c) active region cross section of device A, overlaid with contour plots of the electric field profiles |E_x| for the first two optical modes^[95]

Fig. 7. (a) Top-view schematic of the QCL array and AWG; (b) micrograph of a multi-spectral DFB laser^[103]