Chinese Journal of Liquid Crystals and Displays, Volume. 37, Issue 7, 861(2022)
Design of multi-channel real-time video processing system based on FPGA
Fig. 1. Internal logic block diagram of the video sending card FPGA
Fig. 2. Internal logic block diagram of the video receiving card FPGA
Fig. 3. Logic design diagram of the bilinear interpolation algorithm
Fig. 13. Effect of image superimposition and fusion algorithm implemented on FPGA
Table 1. On-chip power consumption of the video sending card
View tableView in ArticleTable 1. On-chip power consumption of the video sending card
On-chip Power/W Utilization/% Clocks 0.071 5 Signals 0.068 5 Logic 0.057 4 BRAMs 0.106 7 DSPs 0.012 1 PLLs 0.092 6 MMCM 0.202 14 PHASER 0.250 17 IOs 0.616 42 XADS 0.004 <1 DeviceStatic 0.108 7
Table 2. On-chip power consumption of the video receiving card
View tableView in ArticleTable 2. On-chip power consumption of the video receiving card
On-chip Power/W Utilization/% Clocks 0.231 7 Signals 0.176 5 Logic 0.151 4 BRAMs 0.417 12 DSPs 0.035 1 PLLs 0.133 4 MMCM 0.558 16 PHASER 0.661 19 IOs 1.154 33 XADS 0.004 <1 DeviceStatic 0.189 5
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Fei YAN, Zhao-dong DING, Yin-ping LIU, Wei CHEN, Jia LIU. Design of multi-channel real-time video processing system based on FPGA[J]. Chinese Journal of Liquid Crystals and Displays, 2022, 37(7): 861
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Received: Jan. 1, 2022
Accepted: --
Published Online: Jul. 7, 2022
The Author Email: Jia LIU (liujia@nuist.edu.cn)
