Design of Data Reconciliation System Based on FPGA Heterogeneous Computing

Table 1. FPGA resource utilization of unroll loops
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Table 1. FPGA resource utilization of unroll loops
Programmable logic resource Logic ALUTs FFs RAMs DSPs
Original resource utilization /% 33 17 17 28 10
Resource utilization of unroll loops /% 61 31 32 44 49

Table 2. Memory models corresponding to FPGA resources
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Table 2. Memory models corresponding to FPGA resources
FPGA resource Arguments Corresponding memory model
External memory 8 GB DDR3 Global memory
Part of external memory 16 kB Constant memory
M9K memory 2.5 MB Local memory
Register 938880 Private memory

Table 3. Performance comparison of work-groups of different sizes
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Table 3. Performance comparison of work-groups of different sizes
Work-group size 50 100 200 500 800 1000
A_ve-time /s 4.32 3.05 2.48 2.24 2.32 2.39
S_peed /（kbit·s^-1） 46.35 65.48 80.63 89.29 86.21 83.68

Table 4. Experimental results of CPU platform and CPU/FPGA heterogeneous platform at different code rates

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Table 4. Experimental results of CPU platform and CPU/FPGA heterogeneous platform at different code rates

R_ate	CPU			CPU/FPGA
R_ate	R_SN /dB	A_ve-time /s	S_peed /（kbit·s^-1）	R_SN /dB	A_ve-time /s	S_peed /（kbit·s^-1）
0.1	0.15	3.9544	50.58	0.15	0.9858	202.88
0.2	0.33	4.4656	44.79	0.33	1.1108	180.05
0.3	0.54	5.8448	34.22	0.55	1.3223	151.25
0.4	0.79	9.9538	20.09	0.81	2.0494	97.59
0.5	1.38	14.1742	14.11	1.43	2.8578	69.98
0.6	2.42	17.7690	11.26	2.49	3.4542	57.90
0.7	4.67	18.2994	10.93	4.80	3.5741	55.96

Table 5. Comparison of key quantity between CPU platform and CPU/FPGA platform at different code rates

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Table 5. Comparison of key quantity between CPU platform and CPU/FPGA platform at different code rates

R_ate	CPU				CPU/FPGA
R_ate	R_SN /dB	β /%	R_ate-bit /（kbit·s^-1）	D_istance /km	R_SN /dB	β /%	R_ate-bit /（kbit·s^-1）	D_istance /km
0.1	0.15	99.19	19.08	49.25	0.15	99.19	19.08	49.25
0.2	0.33	97.22	14.29	48.35	0.33	97.22	14.29	48.35
0.3	0.54	96.32	12.09	47.30	0.55	94.90	8.62	47.25
0.4	0.79	95.24	9.46	46.05	0.81	93.46	5.11	45.95
0.5	1.38	79.94	-27.85	43.10	1.43	78.07	-32.41	42.85
0.6	2.42	67.64	-57.82	37.90	2.49	66.55	-60.49	37.55
0.7	4.67	55.93	-86.39	26.65	4.80	55.20	-88.15	26.00

Table 6. Experimental results of CPU/GPU and CPU/FPGA heterogeneous platforms at different code rates
View table
Table 6. Experimental results of CPU/GPU and CPU/FPGA heterogeneous platforms at different code rates
R_ate CPU/GPU CPU/FPGA
R_SN /dB A_ve-time /s S_peed /（kbit·s^-1） R_SN /dB A_ve-time /s S_peed /（kbit·s^-1）
0.3 0.55 2.84 70.42 0.55 1.3223 151.25
0.4 1.00 2.90 68.97 0.81 2.0494 97.59

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Jiasen Liu, Dabo Guo, Tianhao Guo, Xianzhong Li, Yujie Wang, Yingxiu Meng. Design of Data Reconciliation System Based on FPGA Heterogeneous Computing[J]. Acta Optica Sinica, 2023, 43(2): 0227001

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Paper Information

Category: Quantum Optics

Received: Jun. 9, 2022

Accepted: Jul. 21, 2022

Published Online: Feb. 7, 2023

The Author Email: Guo Dabo (dabo_guo@sxu.edu.cn)

DOI:10.3788/AOS0227001

Topics

laser devices and laser physics

Lasers and Laser Optics

Laser physics

laser manufacturing

Instrumentation, Measurement and Metrology

Table 1. FPGA resource utilization of unroll loops

Table 1. FPGA resource utilization of unroll loops

Table 2. Memory models corresponding to FPGA resources

Table 2. Memory models corresponding to FPGA resources

Table 3. Performance comparison of work-groups of different sizes

Table 3. Performance comparison of work-groups of different sizes

Table 4. Experimental results of CPU platform and CPU/FPGA heterogeneous platform at different code rates

Table 4. Experimental results of CPU platform and CPU/FPGA heterogeneous platform at different code rates

Table 5. Comparison of key quantity between CPU platform and CPU/FPGA platform at different code rates

Table 5. Comparison of key quantity between CPU platform and CPU/FPGA platform at different code rates

Table 6. Experimental results of CPU/GPU and CPU/FPGA heterogeneous platforms at different code rates

Table 6. Experimental results of CPU/GPU and CPU/FPGA heterogeneous platforms at different code rates