<trans-title xml:lang="en">Comparison of neutron induced single event upsets in 14 nm FinFET and 65 nm planar static random access memory devices</trans-title>

Zhan-Gang Zhang; Zhi-Feng Lei; Teng Tong; Xiao-Hui Li; Song-Lin Wang; Tian-Jiao Liang; Kai Xi; Chao Peng; Yu-Juan He; Yun Huang; Yun-Fei En

doi:10.7498/aps.69.20191209

Acta Physica Sinica, Volume. 69, Issue 5, 056101-1(2020)

Comparison of neutron induced single event upsets in 14 nm FinFET and 65 nm planar static random access memory devices

Zhan-Gang Zhang¹, Zhi-Feng Lei^1、*, Teng Tong², Xiao-Hui Li², Song-Lin Wang³, Tian-Jiao Liang³, Kai Xi⁴, Chao Peng¹, Yu-Juan He¹, Yun Huang¹, and Yun-Fei En¹

Author Affiliations

¹Science and Technology on Reliability Physics and Application of Electronic Component Laboratory, China Electronic Product Reliability and Environmental Testing Research Institute, Guangzhou 510610, China

²Institute of High Energy Physics, Chinese Academy of Sciences, Beijing 100049, China

³Spallation Neutron Source Science Center, Dongguan 523803, China

⁴Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

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Figures & Tables(15)

Fig. 1. Experimental setup (neutron beam channel is loca-ted behind the test board, and aligned with the device under test).

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Fig. 2. Neutron energy spectrum of the experimental terminal.

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Fig. 3. Comparison of neutron (E > 10 MeV) SEU cross section of 65 nm planar and 14 nm FinFET SRAM devices.

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Fig. 4. Comparison of thermal neutron SEU cross section of 65 nm planar and 14 nm FinFET SRAM devices.

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Fig. 5. Relationship between LET value and energy of (a) Li ion and (b) He ion in silicon material.

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Fig. 6. Heavy ion experiment results of 14 nm FinFET SRAM.

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Fig. 7. Comparison of neutron MBU ratio of 65 nm planar and 14 nm FinFET SRAM devices (using the full spectrum in Fig. 2).

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Fig. 8. Reverse analysis of 14 nm FinFET SRAM: (a) Cross section; (b) memory area image.

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Fig. 9. Reverse analysis of 65 nm SRAM: (a) Cross section; (b) memory area image.

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Fig. 10. 14 MeV and 1600 MeV neutron induced secondary particle distribution in the device SV (W material in the device model is replaced by silica).

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Fig. 11. 14 MeV and 1600 MeV neutron induced secondary particle distribution in the device SV (real device model).

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Fig. 12. The LET value and range of secondary particles generated by 14 MeV and 1600 MeV neutrons in the device SV.

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Fig. 13. The deposition charge of 14 MeV and 1600 MeV neutrons in the device SV.

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Table 1.
Parameters of devices under test.
被测器件参数
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Table 1.
Parameters of devices under test.
被测器件参数
编号 SRAM工艺型号容量供电电压(core)/V 封装形式
1# 65 nm平面 CY7 C1663 KV18 8 Mb × 18 1.8 BGA, 非倒装
2# 14 nm FinFET — 8 Mb × 16 0.8 BGA, 倒装

Table 2.
Memory cell size and SV parameters for the 14 nm FinFET SRAM and 65 nm SRAM devices.
14 nm FinFET SRAM和65 nm SRAM的存储单元尺寸和灵敏区参数

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Table 2.
Memory cell size and SV parameters for the 14 nm FinFET SRAM and 65 nm SRAM devices.
14 nm FinFET SRAM和65 nm SRAM的存储单元尺寸和灵敏区参数

器件	存储单元尺寸/ μm × μm	灵敏区尺寸/ μm × μm	灵敏区厚度/nm	重离子LET阈值/ MeV·cm²·mg^–1	临界电荷/fC
14 nm FinFET SRAM	0.37 × 0.18	0.08 × 0.03	45	0.1	0.05
65 nm SRAM	1.0 × 0.5	0.20 × 0.19	450	0.22 ^[18]	1^[19]

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Zhan-Gang Zhang, Zhi-Feng Lei, Teng Tong, Xiao-Hui Li, Song-Lin Wang, Tian-Jiao Liang, Kai Xi, Chao Peng, Yu-Juan He, Yun Huang, Yun-Fei En. Comparison of neutron induced single event upsets in 14 nm FinFET and 65 nm planar static random access memory devices[J]. Acta Physica Sinica, 2020, 69(5): 056101-1

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Paper Information

Category:

Received: Aug. 8, 2019

Accepted: --

Published Online: Nov. 18, 2020

The Author Email:

DOI:10.7498/aps.69.20191209

Topics

Nuclear physics

Particles and fields

Particle and nuclear astrophysics and cosmology

Table 1. Parameters of devices under test.被测器件参数

Table 1. Parameters of devices under test.被测器件参数

Table 2. Memory cell size and SV parameters for the 14 nm FinFET SRAM and 65 nm SRAM devices.14 nm FinFET SRAM和65 nm SRAM的存储单元尺寸和灵敏区参数

Table 2. Memory cell size and SV parameters for the 14 nm FinFET SRAM and 65 nm SRAM devices.14 nm FinFET SRAM和65 nm SRAM的存储单元尺寸和灵敏区参数

Table 1.
Parameters of devices under test.
被测器件参数

Table 1.
Parameters of devices under test.
被测器件参数

Table 2.
Memory cell size and SV parameters for the 14 nm FinFET SRAM and 65 nm SRAM devices.
14 nm FinFET SRAM和65 nm SRAM的存储单元尺寸和灵敏区参数

Table 2.
Memory cell size and SV parameters for the 14 nm FinFET SRAM and 65 nm SRAM devices.
14 nm FinFET SRAM和65 nm SRAM的存储单元尺寸和灵敏区参数