Journal of Semiconductors, Volume. 41, Issue 6, 062403(2020)

Variation tolerance for high-speed negative capacitance FinFET SRAM bit cell

Yaqian Qian1, Shushan Qiao1,2, and Rongqiang Yang1
Author Affiliations
  • 1University of Chinese Academy of Science, Beijing 100049, China
  • 2Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China
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    Figures & Tables(9)
    (Color online) the structure of NC-FinFET.
    (Color online) The subthreshold swing improved by NC compared to the baseline.
    The schematic of traditional 6T SRAM-cell.
    The simulation flow chart for analysis the performance variation for the 6T SRAM, and the compact model is the BSIM-CMG cooperating L-K equations.
    (Color online) The VT mismatch between n-type and p-type NC-FinFET under the same process: when the thickness of ferroelectric material increases, the mismatch gets worse.
    (Color online) (a) Read speed, (b) leakage, (c) SNM, and (d) WM of NC-FinFET SRAM influenced by the thickness of ferroelectric material.
    (Color online) (a) Read speed, (b) leakage, (c) SNM, and (d) WM of NC-FinFET SRAM influenced by the fin number of baseline with fixed FE thickness 3 nm.
    (Color online) (a) Read speed, (b) leakage, (c) SNM, and (d) WM of NC-FinFET SRAM influenced by the channel length of baseline with one fin.
    (Color online) (a) Read speed, (b) leakage, (c) SNM, and (d) WM of NC-FinFET SRAM influenced by temperature with one fin and supply voltage ranges from 0.5 to 0.7 V.
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    Yaqian Qian, Shushan Qiao, Rongqiang Yang. Variation tolerance for high-speed negative capacitance FinFET SRAM bit cell[J]. Journal of Semiconductors, 2020, 41(6): 062403

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    Paper Information

    Category: Articles

    Received: Aug. 31, 2019

    Accepted: --

    Published Online: Sep. 10, 2021

    The Author Email:

    DOI:10.1088/1674-4926/41/6/062403

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