A cryogenic 3.3-V supply, 1.6% 3<i>σ</i>-accuracy all-CMOS voltage reference with 58-dB PSR@10 kHz in 0.18-<i>μ</i>m CMOS

Yupeng Yuan; Yi Zhuo; Jianjun Tu; Qingjiang Xia; Yan Zhang; Wengao Lu; Xiangyang Li; Ding Ma

doi:10.1088/1674-4926/24120039

Journal of Semiconductors, Volume. 46, Issue 8, 082201(2025)

A cryogenic 3.3-V supply, 1.6% 3σ-accuracy all-CMOS voltage reference with 58-dB PSR@10 kHz in 0.18-μm CMOS

Yupeng Yuan^1,2, Yi Zhuo³, Jianjun Tu⁴, Qingjiang Xia³, Yan Zhang¹, Wengao Lu³, Xiangyang Li^1、*, and Ding Ma^1、**

¹National Key Laboratory of Infrared Detection Technologies, Shanghai Institute of Technical Physics of the Chinese Academy of Sciences, Shanghai 200083, China

²School of Information Science and Technology, Shanghaitech University, Shanghai 201210, China

³National Key Laboratory of Science and Technology on Micro/Nano Fabrication, School of Integrated Circuits, Peking University, Beijing 100871, China

⁴Naval Research Institute, Shanghai 200235, China

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Fig. 1. Principle of reference voltage generation.

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Fig. 2. (a) Schematic of the proposed voltage reference. (b) Schematic of the inverter-type startup circuit.

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Fig. 3. Simulated temperature dependence of $V_{REF}$ for $V_{DD} = 3.3 V$ .

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Fig. 4. (Color online) (a) Cryogenic chip test setup for the voltage reference circuit measurements. (b) Die photograph. (c) Summary table of voltage reference circuit.

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Fig. 5. Measured temperature dependence of $V_{REF}$ for $V_{DD} = 3.3 V$ .

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Fig. 6. (Color online) Monte Carlo simulation of process manufacturing variations.

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Fig. 7. (a) Measured supply dependence of $V_{REF}$ . (b) Measured PSR.

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Table 1. Performance summary and comparison with state-of-art.

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Table 1. Performance summary and comparison with state-of-art.

Pameters	This work	JSSC 2024^[10]			SSCL 2020^[11]	TCAS-II^[17]
*Estimation based on Monte Carlo simulation.
Process	TSMC 180 nm 1P5M CMOS	TSMC 40 nm 1P7M CMOS	TSMC 40 nm 1P7M CMOS	TSMC 40 nm 1P7M CMOS	28 nm FDSOI CMOS	130 nm CMOS
Process	TSMC 180 nm 1P5M CMOS	NMOS	PMOS	DTMOS	28 nm FDSOI CMOS	130 nm CMOS
Temperature range (K)	30−300	4.2−300	4.2−300	4.2−300	4.2−300	253−398
V_REF (V)	1.2	300 K: 0.484.2 K: 0.48	300 K: 0.544.2 K: 0.71	300 K: 0.634.2 K: 0.60	300 K: 0.4854.2 K: 0.685	0.2
Supply voltage (V)	2.7−3.6	0.96−1.1	0.99−1.1	0.98−1.1	1.21.8	0.5−1.3
Total power (µW)	300 K: 1830 K: 1	300 K: 13.74.2 K: 5.1	300 K: 14.94.2 K: 8.2	300 K: 15.14.2 K: 7.8	300 K: 15.84.2 K: 13.9	300 K: 1.9
3σ_mean (%)	1.6*	1.2	2.6	2.7	N.A.	1.58
TC (ppm/K)	67.5	111	547	475	1214	22.3
BJT type	NO	NO	NO	NO	NO	YES
PSR (dB)	58@10 kHz	N.A.	N.A.	N.A.	51@DC	75@DC
Line regulation (%/V)	30 K: 0.67	300 K: 2.24.2 K: 1.3	300 K: 2.04.2 K: 2.6	300 K: 1.34.2 K: 2.7	300 K: 0.44.2 K: 0.6	N.A.
Area (mm²)	0.0035	0.006	0.009	0.009	0.041	0.052
Measure or simulation	Measure	Measure	Measure	Measure	Measure	Simulation

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Yupeng Yuan, Yi Zhuo, Jianjun Tu, Qingjiang Xia, Yan Zhang, Wengao Lu, Xiangyang Li, Ding Ma. A cryogenic 3.3-V supply, 1.6% 3σ-accuracy all-CMOS voltage reference with 58-dB PSR@10 kHz in 0.18-μm CMOS[J]. Journal of Semiconductors, 2025, 46(8): 082201

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Paper Information

Category: Research Articles

Received: Dec. 30, 2024

Accepted: --

Published Online: Aug. 27, 2025

The Author Email: Xiangyang Li (XYLi), Ding Ma (DMa)

DOI:10.1088/1674-4926/24120039

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