A cryogenic 3.3-V supply, 1.6% 3<i>σ</i>-accuracy all-CMOS voltage reference with 58-dB PSR@10 kHz in 0.18-<i>μ</i>m CMOS

Yupeng Yuan; Yi Zhuo; Jianjun Tu; Qingjiang Xia; Yan Zhang; Wengao Lu; Xiangyang Li; Ding Ma

doi:10.1088/1674-4926/24120039

Introduction

Voltage reference circuits represent a pivotal component within contemporary integrated circuits, providing a stable voltage reference that is impervious to temperature variations and supply voltage fluctuations. These circuits are extensively employed in analog, digital, and mixed-signal systems to guarantee consistent and reliable performance under a diverse range of operating conditions^[1−5]. The traditional bandgap reference design, typically incorporates bipolar junction transistors (BJTs), has undergone extensive study and optimization over the years.

However, non-idealities, such as finite current gain, parasitic base resistance and non-unity emission coefficient, deteriorate the accuracy of the BJTs characteristics, which would lead to the failure of bandgap reference circuits at low temperature^{[6, 7]}.

Low-temperature bandgap circuits have emerged as a crucial area of research due to their essential applications in cryogenic electronics, quantum computing, and space exploration. Operating at temperatures as low as 4 K presents unique challenges, including increased thermal noise and altered carrier mobility, which adversely affect the performance of traditional bandgap references^{[8, 9]}. Recent developments in low-temperature bandgap circuits have concentrated on mitigating these effects through circuit design techniques such as dynamic element matching (DEM) techniques^[10], and the use of advanced technology with stable electrical properties^[11]. These efforts enable voltage circuits to operate over an ultra-wide temperature range from 4 to 300 K while maintaining an excellent TC to achieve a stable reference voltage.

Achieving high 3σ-accuracy and maintaining performance across a wide temperature range remain active areas of research. This paper presents a novel all-CMOS bandgap reference circuit that operates effectively from 30 to 300 K. The 30−300 K temperature range is critical for space exploration, cryogenic electronics, and high-performance sensor systems, as it aligns with the operational conditions of infrared focal plane arrays (FPAs) and readout integrated circuits (ROICs) used in astronomical observations^[12]. Cryogenic cooling in such applications reduces thermal noise and enhances detection sensitivity, necessitating a stable and precise voltage reference for sensor biasing and signal processing. Furthermore, the proposed voltage reference is highly applicable in low-dropout regulators (LDOs) for deep-space missions and high-energy physics experiments, ensuring stable power regulation under extreme temperature conditions while maintaining low power consumption and high temperature stability for FPAs, sensor arrays, and precision analog front-end circuits.

The core concept of the proposed voltage reference is illustrated in Fig. 1. Two current source circuits are employed to generate proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) currents. By combining these currents, a temperature-independent reference current is produced and subsequently converted to voltage, exhibiting an excellent temperature coefficient and high 3σ-accuracy. This work is implemented based on device models derived from low-temperature measurements and existing models^[13]. Furthermore, the proposed design incorporates a current subtraction technique for temperature compensation, eliminating the need for BJTs to further minimize area and power consumption. Unlike previous studies that primarily depend on simulation results, this work is substantiated through rigorous empirical testing, underscoring its practical applicability and reliability in real-world scenarios.

Figure 1.Principle of reference voltage generation.

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The rest of this brief is structured as follows: Section 2 details the implementation of the proposed voltage reference architectures. Section 3 presents the experimental results of reference circuits measured over a wide temperature range. And finally, Section 4 concludes the brief.

Circuit design

Working principle

A MOSFET operating in the weak inversion region exhibits exponential I−V characteristics, the drain current $I_{D}$ can be formulated as:

1 $I_{D} = μ C_{ox} S (n - 1) V_{T}^{2} exp (\frac{V_{GS} - V_{TH}}{n V_{T}}),$

where $μ$ is the carrier mobility, $C_{ox}$ is the gate oxide capacitance per unit area, $S$ is defined as $S = W / L$ , $W$ and $L$ are the width and length of the MOSFET, $n$ is the nonideality factor, and $V_{T}$ is the thermal voltage.

The proposed architecture, as shown in Fig. 2(a), comprises the current source circuit, the reference voltage generator and the TC compensation circuit. An inverter-type start-up circuit is introduced to ensure the well-defined quiescent operation point in the entire temperature region. Fig. 2(b) illustrates an inverter-type start-up circuit introduced to ensure a well-defined quiescent operating point across the entire temperature range.

Figure 2.(a) Schematic of the proposed voltage reference. (b) Schematic of the inverter-type startup circuit.

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The voltage relationship within the current source circuit can be expressed as:

2 $V_{GS,N1} = V_{GS,N2} + V_{R} .$

Since MN1 and MN2 work in the weak inversion region, the voltage across the resistor can be given by:

3 $V_{R} = n_{N} V_{T} ln \frac{S_{N2}}{S_{N1}},$

where $S_{N1}$ and $S_{N2}$ are the aspect ratios of MN1 and MN2.

The drain current of MP2 and MN2 are expressed as:

4 $I_{BIAS} = \frac{n_{N} V_{T} ln \frac{S_{N2}}{S_{N1}}}{R} = \frac{n_{N} V_{T} ln \frac{S_{N2}}{S_{N1}}}{R_{0} + δ T},$

where $δ$ is a constant, $R_{0}$ is the resistance value at room temperature. By appropriately adjusting $S_{N2} / S_{N1}$ , the PTAT characteristic of $I_{BIAS}$ can be controlled.

The current mirrors, comprising transistors (MP3−MP6) operating in the weak inversion region, effectively replicate $I_{BIAS}$ to $I_{REF}$ with a proportion of 4 : 1. Then, $I_{REF}$ flows through gate−drain shorted PMOS (MP7) and NMOS couple (MN3 and MN4)^[14]. It has been demonstrated that the saturation current through of MP7 is $2 I_{REF}$ . Consequently, $V_{SG,P7}$ is given as:

5 $V_{SG,P7} = | V_{TH,P7} | + \sqrt{\frac{4 I_{REF}}{μ_{p} C_{ox} S_{P7}}} .$

According to $I_{BIAS} : I_{REF} = 4 : 1$ and Eq. (4), it can be derived that:

6 $V_{SG,P7} = | V_{TH,P7} | + \sqrt{\frac{n_{N} V_{T} ln \frac{S_{N2}}{S_{N1}}}{μ_{p} C_{ox} S_{P7} (R_{0} + δ T)}} .$

Connecting the substrate of MP7 to the source of MP8, rather than to its own source, would induce the substrate bias effect. The threshold voltage of MP7 can be expressed as:

7 $| V_{TH} | = | V_{th0} | + γ (\sqrt{| 2 ϕ_{F} + V_{BS} |} - \sqrt{2 ϕ_{F}}),$

where $V_{th0}$ is the threshold voltage without the substrate bias and exhibits the CTAT characteristic, $γ$ is the substrate bias coefficient which is negative in PMOS transistors, $ϕ_{F}$ is the substrate Fermi potential.

According to Eq. (6), $V_{BS}$ of MP7 can be given by:

8 $\begin{array}{l} V_{BS} = V_{SG,P8} - V_{SG,P7} = \\ (\sqrt{\frac{1}{S_{P8}}} - \sqrt{\frac{1}{S_{P7}}}) (\sqrt{\frac{n_{N} V_{T} ln \frac{S_{N2}}{S_{N1}}}{μ_{p} C_{ox} (R_{0} + δ T)}}) . \end{array}$

By adjusting $S_{P7}$ and $S_{P8}$ , $V_{BS}$ can be less than zero. Therefore, $γ (\sqrt{| 2 ϕ_{F} + V_{BS} |} - \sqrt{2 ϕ_{F}})$ exhibits the PTAT characteristic, $| V_{TH} |$ consists of the PTAT and CTAT components.

According to the established $α - power$ model^[15], both $μ$ and $V_{TH}$ are temperature dependent, these parameters can be formulated as:

9 $μ (T) = k_{μ} T^{- β},$

and

10 $| V_{TH} (T) | = | V_{TH 0} | - η T,$

where $k_{μ}$ is a constant, $V_{TH 0}$ is the extrapolated threshold voltage at $T = 0 K$ , $η$ is a constant which represents the temperature coefficient of $V_{TH}$ . Eq. (5) can be further expressed as:

11 $V_{SG,P7} = | V_{TH 0, P 7} | - η T + \sqrt{\frac{n_{N} V_{T} ln \frac{S_{N2}}{S_{N1}}}{k_{μ} T^{- β} C_{ox} S_{P7} (R_{0} + δ T)}} .$

It is pertinent to highlight that $V_{SG,P7}$ is a CTAT voltage, owing to the fact that the coefficient $η$ typically exceed the thermal dependency of $V_{T}$ .

Moreover, MN3 and MN4 operate in the weak inversion region. Employing Eq. (1) and disregarding variations in $V_{TH}$ , the $Δ V_{GS}$ between MN3 and MN4 is presented as follow:

12 $Δ V_{GS} = n_{N} V_{T} ln \frac{S_{N3}}{S_{N4}} .$

The output voltage $V_{REF}$ can be expressed as:

13 $V_{REF} = V_{SG,P7} + Δ V_{GS} .$

Compensation

Merging Eqs. (11)−(13), $V_{REF}$ is defined as follows:

14 $\begin{array}{l} V_{REF} = & | V_{TH 0, P 7} | - η T \\ + & \sqrt{\frac{n_{N} V_{T} ln \frac{S_{N2}}{S_{N1}}}{k_{μ} T^{- β} C_{ox} S_{P7} (R_{0} + δ T)}} + n_{N} V_{T} ln \frac{S_{N3}}{S_{N4}} . \end{array}$

In conclusion, temperature characteristic of $V_{REF}$ can be optimized by adjusting the $W / L$ of R, MP7, MN1, MN2, MN3 and MN4.

By differentiating with respect to temperature, $\frac{d V_{REF}}{d T}$ is derived as:

15 $\frac{d V_{REF}}{d T} = ξ + ω \frac{T^{\frac{β - 1}{2}}}{{(R_{0} + δ T)}^{\frac{3}{2}}},$

where $ξ = - η + \frac{n_{N} k}{q} ln \frac{S_{N3}}{S_{N4}}$ and $ω = \frac{(β R_{0} + δ β T + R_{0})}{2}$ , the magnitude of $δ β$ is so negligible that $ω$ can be regarded as a constant. As can be seen from Eq. (15), the first derivative of the voltage $V_{REF}$ exhibits a zero crossing within the range from 30 to 300 K, suggesting that $V_{REF}$ exhibits first-order compensation. The gates of MP7 and MP8 are connected to the drain of MN5 instead of being directly tied to ground, which enhances PSR by providing improved noise immunity and stability against supply variations.

The voltage curve of the proposed circuit varying with temperature is depicted in Fig. 3. The TC of $V_{REF}$ with compensation can be 52.5 ppm/K in the range from 30 to 300 K.

Figure 3.Simulated temperature dependence of $V_{REF}$ for $V_{DD} = 3.3 V$ .

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Measure results

Measurement setup

The proposed circuit is fabricated in the 0.18-µm standard CMOS process. To establish a cryogenic-temperature test environment, a refrigeration machine is employed to cool the designed chip down to 30 K. The cryogenic test setup is presented in Fig. 4(a), including several crucial components: a refrigerating machine, a vacuum dewar, a customized conversion PCB testing board and a source measure unit with an input impedance greater than 10 GΩ.

Figure 4.(Color online) (a) Cryogenic chip test setup for the voltage reference circuit measurements. (b) Die photograph. (c) Summary table of voltage reference circuit.

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During the testing process, a customized PCB board is enclosed in a vacuum dewar, with the ambient temperature inside the dewar regulated by the cryocooler. The output voltage is transmitted from the cryogenic chip to the measure unit. To ensure a high-quality signal transfer within the system, coaxial cables are used between the PCB board and the measure unit. Fig. 4(b) presents a die photograph of the custom test-chip, along with a summary table of the measured performance in Fig. 4(c).

Measure results

Fig. 5 shows the measured temperature dependence of $V_{REF}$ . The average value of $V_{REF}$ is 1.2025 V, with the voltage variation across the temperature range from 30 to 300 K is approximately 20.9 mV, resulting in the calculated TC is about 67.5 ppm/K.

Figure 5.Measured temperature dependence of $V_{REF}$ for $V_{DD} = 3.3 V$ .

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The response of $V_{REF}$ to fabrication process variations is illustrated in Fig. 6. The average value of $V_{REF}$ is approximately 1.21 V, with a standard deviation of 19.33 mV, resulting in a variation coefficient $σ / μ$ of about $1.6 %$ . The stability of $V_{REF}$ demonstrates a high sensitivity to process variations, primarily due to its dependence on $V_{TH}$ , which shows a deviation of approximately a few millivolts in the statistical analysis of the process. As stated in the document^[16], the measured values are significantly lower than the predictions obtained through Monte Carlo simulations. As the circuits are fabricated on the same wafer, the inter-chip discrepancy is exaggerated in the simulations, leading to the reduction of reference voltage variation.

Figure 6.(Color online) Monte Carlo simulation of process manufacturing variations.

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Fig. 7(a) presents the dependence of $V_{REF}$ on $V_{DD}$ at 30 K. revealing the minimum required supply voltage is 2.7 V. The variation of $V_{REF}$ is 7.2 mV over $V_{DD}$ range of 2.7 to 3.6 V. Furthermore, Fig. 7(b) illustrates the PSR performance of $V_{REF}$ under $V_{DD} = 3.3 V$ at 30 K, with the PSR of $V_{REF}$ , achieving 58 dB at 10 kHz and 46 dB at 10 MHz.

Figure 7.(a) Measured supply dependence of $V_{REF}$ . (b) Measured PSR.

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Table 1 presents performance comparison with other works documented in references^{[10, 11, 17]}. The proposed circuit exhibits lower power consumption and area compared to the works^{[10, 11]} at 30 K. Additionally, it achieves superior TC performance than the works^{[10, 11]}, while maintaining a PSR of approximately 58 dB at 10 kHz.

Table 1. Performance summary and comparison with state-of-art.

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Table 1. Performance summary and comparison with state-of-art.

Pameters	This work	JSSC 2024^[10]			SSCL 2020^[11]	TCAS-II^[17]
*Estimation based on Monte Carlo simulation.
Process	TSMC 180 nm 1P5M CMOS	TSMC 40 nm 1P7M CMOS	TSMC 40 nm 1P7M CMOS	TSMC 40 nm 1P7M CMOS	28 nm FDSOI CMOS	130 nm CMOS
Process	TSMC 180 nm 1P5M CMOS	NMOS	PMOS	DTMOS	28 nm FDSOI CMOS	130 nm CMOS
Temperature range (K)	30−300	4.2−300	4.2−300	4.2−300	4.2−300	253−398
V_REF (V)	1.2	300 K: 0.484.2 K: 0.48	300 K: 0.544.2 K: 0.71	300 K: 0.634.2 K: 0.60	300 K: 0.4854.2 K: 0.685	0.2
Supply voltage (V)	2.7−3.6	0.96−1.1	0.99−1.1	0.98−1.1	1.21.8	0.5−1.3
Total power (µW)	300 K: 1830 K: 1	300 K: 13.74.2 K: 5.1	300 K: 14.94.2 K: 8.2	300 K: 15.14.2 K: 7.8	300 K: 15.84.2 K: 13.9	300 K: 1.9
3σ_mean (%)	1.6*	1.2	2.6	2.7	N.A.	1.58
TC (ppm/K)	67.5	111	547	475	1214	22.3
BJT type	NO	NO	NO	NO	NO	YES
PSR (dB)	58@10 kHz	N.A.	N.A.	N.A.	51@DC	75@DC
Line regulation (%/V)	30 K: 0.67	300 K: 2.24.2 K: 1.3	300 K: 2.04.2 K: 2.6	300 K: 1.34.2 K: 2.7	300 K: 0.44.2 K: 0.6	N.A.
Area (mm²)	0.0035	0.006	0.009	0.009	0.041	0.052
Measure or simulation	Measure	Measure	Measure	Measure	Measure	Simulation

Conclusion

This brief presents a cryogenic bandgap reference voltage circuit. Compared to prior cryogenic voltage reference designs, this approach eliminates the need for BJTs or special MOSFETs. The proposed circuit demonstrates a TC of 67.5 ppm/K with a 3σ-accuracy of 1.6% across a temperature range of 30 to 300 K. Additionally, most of the MOSFETs operate in the weak inversion region, enabling energy-efficient performance. Current mirrors and the output stage are capable of optimizing the current source performance and refining TC across different process manufacturing variations. The proposed voltage reference is highly applicable in space exploration, ensuring stable power regulation under extreme temperature conditions while maintaining low power consumption and high temperature stability for FPAs, sensor arrays, and precision analog front-end circuits.

Category: Research Articles

Received: Dec. 30, 2024

Accepted: --

Published Online: Aug. 27, 2025

The Author Email: Xiangyang Li (XYLi), Ding Ma (DMa)

DOI:10.1088/1674-4926/24120039