High-power laser diodes (LDs) are crucial for various applications, such as industrial processing, medical cosmetology, laser communication, and high-energy laser weapons^[1–3]. Photonic crystal (PC) LDs are favored due to their compact size, light weight, ease of modulation, high power conversion efficiency (PCE), and narrow divergence angle^[4–7]. However, their output power is often limited by thermal effects. For example, 976 nm high-power PC LDs currently achieve a maximum continuous-wave (CW) output power of 43.03 W at 0°C^[8]. Thermal effects lead to an increase in the temperature of the active region, which in turn raises the threshold current, reduces slope efficiency, induces wavelength redshift, and compromises both reliability and stability^[9–12].

To mitigate these issues, the most direct and effective approach is the advanced package heat dissipation technology^[13,14]. Additionally, optimizing the LD chip epitaxial design can also contribute positively^[15–19]. In this study, we developed a conduction heat dissipation model for PC LDs with a conduction-cooled heat sink mount (CS-mount) package. The finite element method (FEM) was employed to simulate the steady-state thermal characteristics and optimize the design of the transition heat sink and heat sink dimensions. The optimized design achieved an 83.3% reduction in heat sink volume and an 18.2% improvement in heat dissipation. The PC LD, packaged with this optimized heat sink structure, obtained a CW output power of 48.5 W with a thermal resistance of only 1.17 K/W at 20°C and 54.5 W with the maximum PCE of 62.4% at 5°C. To the best of our knowledge, this is the best result reported to date for a high-power PC LD.

The heat generated during the operation of the LD primarily results from non-radiative recombination of carriers, radiative absorption of photons, spontaneous radiative recombination in the active region, and Joule heating in non-active regions^[20–22]. In this study, we developed a thermal model for a 976 nm PC LD using COMSOL Multiphysics software. The steady-state thermal characteristics were solved using the FEM, and the influence of the heat sink structure and material on the thermal performance of the device was analyzed. Optimization of designs is mainly focused on two aspects: radiator size and transition radiator.

The 3D heat dissipation model of a PC LD with the CS-mount package is established based on conductive cooling, as shown in Fig. 1. The heat generated in the chip is mainly transmitted through heat-conducting heat sinks and external cooling structures. To improve the heat dissipation effect more efficiently, the PC LD chip with a 4 mm cavity length and a 350 µm stripe width is mounted P-side down on the Cu heat sink (25mm×25mm×7.5mm). The upper and lower surfaces of the heat sink are coated with a metal layer to prevent the solder from spreading downward. The Cu heat sink serves as the positive electrode of the PC LD, while the negative electrode is drawn from the copper-clad ceramic plate fixed on the heat sink. The materials and parameters of each structural layer are detailed in Table 1.

In the process of simulation with COMSOL software, based on experimental experience and references, several assumptions were made to simplify the calculation^[23,24]: 1)The heat source is concentrated in the active region of the chip, and the secondary heat sources, such as Joule heating, are ignored.2)The output power of a PC LD is 35 W, with thermal power assumed to be 28.64 W (PCE is 55%).3)The heat generated in the active region is only conducted downward to the heat sink through the P-side surface. The radiation heat dissipation and air convection heat dissipation on the chip surface are ignored.4)The bottom surface of the heat sink is in contact with the external cooler and is maintained at 20°C. There is thermal convection between the air and the heat sink surface, and the heat transfer coefficient is 10W/(m2·K).5)The LD is assumed to be in ideal working condition, unaffected by the void thermal effect of the patch layer, and the thermal and mechanical parameters for all materials are assumed to be temperature independent.

The cavity length direction is defined along the length of the heat sink, the stripe width direction along the width of the heat sink, and the epitaxial direction along the thickness of the heat sink. Since the chip is in direct contact with the heat sink, the thermal resistance of the LD is strongly influenced by the heat sink’s dimensions. To balance effective heat dissipation and device miniaturization, the heat sink’s volume must be optimized, which also contributes to reducing the overall cost of the device. In this study, the variation of the junction temperature and thermal resistance is analyzed to determine the optimal structural parameters of the heat sink. The thermal resistance Rth is calculated by Rth=ΔTΔPth=(ΔλΔT)−1(ΔλΔPth),(1)where ΔT is the temperature rise in the active region of the LD, ΔPth is the thermal power of the LD, and Δλ is the red shift of the laser wavelength.

First, consider the effect of heat sink length. The heat sink width is fixed at 25 mm, and the thickness is fixed at 7.5 mm. The variation of the LD junction temperature and thermal resistance with the length of the heat sink is then simulated. As shown in Fig. 2(a), when the heat sink length increases from 4 to 14 mm, the junction temperature and thermal resistance decrease rapidly by 4.72°C and 0.16 K/W, respectively. However, beyond 14 mm, further increases in length result in negligible changes in both junction temperature and thermal resistance.

Next, analyze the effect of heat sink width. The length and thickness of the heat sink are fixed at 25 and 7.5 mm, respectively, while the heat sink width is quantitatively increased from 3 to 25 mm. As shown in Fig. 2(b), when the heat sink width increases, the junction temperature decreases from 79.66°C to 59.12°C, and the thermal resistance decreases from 2.08 to 1.37 K/W. Notably, for widths ranging from 3 to 14 mm, the junction temperature and thermal resistance decrease exponentially. However, beyond 14 mm, further increases in width yield minimal improvements in these thermal properties.

Finally, simulate the effect of the heat sink thickness. With the length and width fixed at 25 mm, the heat sink thickness is varied from 1 to 7.5 mm. As shown in Fig. 3, increasing the thickness of the heat sink results in a rise in junction temperature from 50.04°C to 59.12°C, while the thermal resistance increases from 1.05 to 1.37 K/W. A thinner heat sink is preferred for enhanced thermal performance. However, the material’s brittleness must also be taken into account. Consequently, the final dimensions of the CS-mount heat sink are determined to be 14mm×14mm×4mm, achieving an optimal balance among thermal performance, cost, stability, and portability under practical process conditions.

The steady-state thermal characteristics of the traditional and size-optimized CS-mount heat sinks are presented in Fig. 4. The heat generated by the LD chip is primarily conducted to the Cu heat sink, which maintains a lower temperature. For the traditional CS-mounted device, the maximum junction temperature is 59.12°C, while for the size-optimized CS-mounted device, it is 60.37°C. Using Eq. (1), the thermal resistance of the size-optimized device is calculated to be 1.41 K/W, which is only 2.9% higher than that of the traditional CS-mount device (1.37 K/W). However, the size-optimized heat sink achieves an 83.3% reduction in volume compared to the traditional design, significantly enhancing its compactness and practicality.

To address the mismatch in the coefficient of thermal expansion (CTE) between the heat sink material (Cu) and the chip material (GaAs), a transition heat sink is typically introduced between the heat sink and the LD chip. An ideal transition heat sink material should possess high thermal conductivity and match the expansion of the LD chip. Common transition heat sink materials include diamond, SiC, BeO, AlN, and WCu. The parameters of these transition heat sink materials, along with those of Cu and GaAs, are summarized in Table 2.

Among these materials, diamond stands out due to its exceptionally high thermal conductivity and compatibility with the expansion of the LD chip. Using diamond as a transition heat sink significantly reduces the thermal resistance of the LD and enhances its performance. In this setup, the PC LD chip is first mounted P-side down onto a metallized diamond transition heat sink using a 6 µm AuSn solder. It is then soldered onto the optimized Cu heat sink with a 10 µm In solder. The 3D composite heat dissipation model of the PC LD with a diamond transition heat sink is illustrated in Fig. 5(a).

The dimensions of the transition heat sink need to be larger than those of the LD chip. Therefore, the length and width of the transition heat sink are set to 4.5 and 5.3 mm, respectively. The simulation results for the junction temperature and thermal resistance of the device with different thicknesses of diamond transition heat sinks are shown in Fig. 5(b). These results indicate that increasing the thickness of the transition heat sink from 0.1 to 1.2 mm reduces the junction temperature from 58.74°C to 51.58°C and decreases the thermal resistance from 1.35 to 1.10 K/W. However, when the thickness exceeds 0.5 mm, the changes in junction temperature and thermal resistance become minimal.

Based on these findings, the optimal thickness of the diamond transition heat sink is determined to be 0.5 mm. At this thickness, the steady-state thermal characteristic temperature distribution of the composite heat dissipation structure is illustrated in the inset of Fig. 5(b). The maximum junction temperature of the device is 52.21°C, and the thermal resistance is 1.12 K/W, which represents a 20.6% reduction compared to the device without the diamond transition heat sink (1.41 K/W). These results demonstrate that the incorporation of a diamond transition heat sink significantly enhances the heat dissipation performance of the CS-mount packaged PC LD.

We experimentally compared three devices packaged with different structures: Structure A (traditional CS-mount), Structure B (size-optimized CS-mount), and Structure C (size-optimized CS-mount with diamond transition heat sinks). All devices used PC LD chips with a 4 mm cavity length and a 350 µm stripe width. The packaging process includes heat sink and solder cleaning, solder evaporation, welding, and gold wire bonding. The power and spectral test results of the three structured devices at 20°C are shown in Fig. 6. The cold wavelength, approximately 970.20 nm, defined as the wavelength measured at a pulsed current of 5 A (100 µs, 100 Hz), reflects the LD’s state without heat accumulation.

Under the same conditions, Structure C exhibited the highest power and shortest wavelength, indicating superior heat dissipation performance consistent with simulation expectations. A detailed comparison of the performance parameters at 35 W is presented in Table 3. Thermal resistance and temperature increase of the active region are calculated using Eq. (1), with the wavelength temperature drift coefficient Δλ/ΔT taken as 0.28 nm/K^[25]. Compared with Structure A, Structure B with reduced CS-mount heat sink size showed a slight increase in thermal resistance from 1.40 to 1.46 K/W, and the junction temperature in LD increased by 2.25°C. In contrast, the thermal resistance of Structure C with the diamond transition heat sink is decreased from 1.46 to 1.17 K/W, resulting in a relative improvement of 19.9% in thermal performance and a decrease of 9.68°C in junction temperature.

The experimental thermal resistance of all three package structures was slightly higher than the simulated thermal resistance. This discrepancy is possibly due to localized hot spots formed by holes during the encapsulation process, which hinder heat transfer and increase average thermal resistance. In conclusion, by optimizing the design, we reduce the package heat sink volume of the PC LD by 83.3%, while reducing the thermal resistance of the device to 1.17 K/W, i.e., a relative reduction of 16.4%, and the junction temperature by 7.43°C.

To achieve higher output power, the performance of the device with the Structure C package was tested under high injection current. At an injection current of 60 A and 20°C, the CW output power is 48.2 W, and the maximum PCE is 62.2%, as shown in Fig. 7(a). Under the same current at 5°C, the CW output power increases to 54.5 W, and the maximum PCE is 62.4%, as shown in Fig. 7(b). At this time, the horizontal divergence angle of the PC LD is measured to be 15.5° and the vertical divergence angle is 18.2°, which is significantly smaller than that of the ordinary high-power LD^[26,27], as shown in Fig. 8.

In conclusion, we optimized the design of PC LD package structures based on conductive cooling. The simulation results indicate that the heat sink size can be reduced by up to 83.3% while maintaining effective heat dissipation. By introducing a diamond transition heat sink, the heat dissipation efficiency was further improved by 20.6%. Experimentally, we obtained similar results with a 19.9% improvement. Using the optimized structure packaging a 4 mm cavity length and 350 µm stripe width PC LD, we measured a thermal resistance of only 1.17 K/W at 20°C, with a CW output power of 48.2 W. At 5°C, the CW output power reached 54.5 W, and the maximum PCE was 62.4%. The horizontal and vertical divergence angles were 15.5° and 18.2°, respectively. The results of this study provide a basis for optimizing the packaging of high-power LDs, offering significant guidance for practical production.