[1] [1] SHU K L, SANCHEZ-SINENCIO E. CMOS PLL synthesizers: analysis and design ［M］. Boston: Springer, 2007: 201-209.

[3] [3] MANAS K H, TARUN K B. A constant loop bandwidth in delta sigma fractional-N PLL frequency synthesizer with phase noise cancellation ［J］. Integration, 2019, 65: 175-188.

[5] [5] ZHOU B, LI Y, ZHAO F Y. Noise and spur comparison of delta-sigma modulators in fractional-N PLLs ［J］. J Elec Test, 2019, 35(2): 917-923.

[6] [6] CHEN Y, PRAAMSMA L, IVANISEVIC N, et al. A 40 GHz PLL with -925 dBc/Hz in-band phase noise and 104 fs-RMS-jitter ［C］ // IEEE RFIC. Honolulu, HI, USA. 2017: 31-32.