Microelectronics, Volume. 51, Issue 5, 672(2021)
Design of a Sampling Rate Conversion Digital Filter in Hearing Aid Chip
[1] [1] SRIVASTAVA A, ANANTHA R R. A programmable oversampling sigma-delta analog-to-digital converter [C]//48th Midwest Symp Circ & Syst. Covington, KY, USA. 2005: 539-542.
[2] [2] MONDAL A, BHAR S, SRIMANI S, et al. Analytical model of a multi-resolution sample rate re-configurable decimator for SDADC [C]//IEEE Region 10 Symp. Kolkata, India. 2019: 588-592.
[3] [3] GRAYVER E, DANESHRAD B. Low power, area efficient programmable filter and variable rate decimator [C]//IEEE ISCAS. Geneva, Switzerland, 2000: 341-344.
[4] [4] KATES J M. Digital hearing aids [M]. Oxford: Plural Pub, 2008.
[5] [5] GATA D G, SJURSEN W, HOCHSCHILD J R, et al. A 1.1-V 270-μA mixed-signal hearing aid chip [J]. IEEE J Sol Sta Circ, 2002, 37(12): 1670-1678.
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LAN Yuyan, XIAO Wan’ang, WANG Ang, MAO Wenyu. Design of a Sampling Rate Conversion Digital Filter in Hearing Aid Chip[J]. Microelectronics, 2021, 51(5): 672
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Received: Dec. 1, 2020
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Published Online: Feb. 18, 2022
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