Fig. 1. Design of overall drive scheme

Fig. 2. Flow chart of multiplex analog signal timing

Fig. 3. Schematic diagram of the USB chip connection

Fig. 4. Schematic diagram of primary and slave device SPI interface connection

Fig. 5. Schematic diagram of the main control chip and the additional circuit

Fig. 6. Schematic diagram of DAC

Fig. 7. Flow chart of the STM32F429 control software

Fig. 8. Flow chart of STM32F411 control software

Fig. 9. Upper-computer application software interface

Fig. 10. Physical design of hardware design

Fig. 11. Test results