Fig. 1. Schematic diagram of hardware structure of multi-channel phasemeter

Fig. 2. Pilot tone Correction Schematic

Fig. 3. Hardware prototype of multi-channel phasemeter

Fig. 4. Block diagram of phase demodulation algorithm based on DPLL.（MUL: Multiplier; LPF: Low Pass Filter; UDP: User Datagram Protocal）

Fig. 5. Schematic diagram of system arrangement on PL

Fig. 6. Physical prototype of experiment set up

Fig. 7. Phase static linearity test results at different frequencies. (a) 5 MHz; (b) 15 MHz; (c) 20 MHz; (d) 25 MHz;

Fig. 8. Phase dynamic linearity test results at different frequency differences with signal frequency 5 MHz. (a) 0.01 Hz; (b) 0.02 Hz; (c) 0.04 Hz; (d) 0.08 Hz;

Fig. 9. Test results of frequency tracking capability

Fig. 10. Phase noise between different ADC channels

Fig. 11. Phase noise at different frequencies

Fig. 12. Phase noises at different amplitudes