Fig. 1. Schematic of experimental apparatus

Fig. 2. Magnification calibration experimental results. (a) Test target 1951 USAF pattern; (b) element intensity image of group 6; (c) locally magnified intensity image of the 5^th pair of lines

Fig. 3. Schematic of micro-nano one-dimensional grid structure

Fig. 4. Experimental results of transverse resolution calibration. (a) Reproduction phase of group 7 element in the resolution target; (b) phase reproduction of grid with 5 μm line width; (c) phase image reproduction of grid with 1 μm line width

Fig. 5. Measurement results of segment difference standard film. (a) Depth image; (b) height graph

Fig. 6. Chip physical diagram and structure diagram. (a) PDMS chip physical diagram; (b) PDMS chip channel at 50× magnification; (c) enlargement structure diagram of silicon substrate chip channel

Fig. 7. Straight channel holograms under different wavelengths. (a) 632.8 nm channel hologram; (b) 632.8 nm reference hologram; (c) 635.32 nm channel hologram; (d) 635.32 nm reference hologram

Fig. 8. Wrapped phase images of straight channel. (a) Wrapped phase for 632.8 nm; (b) wrapped phase for 635.32 nm; (c) equivalent wavelength phase distribution

Fig. 9. Straight channel measurement results. (a) Depth image; (b) three-dimensional topography image; (c) compare experimental result

Fig. 10. Circular chamber measurement results. (a) Depth image; (b) three-dimensional topography image; (c) sectional graph

Fig. 11. Silicon substrate chip measurement results. (a) Depth image; (b) three-dimensional topography image; (c) sectional graph