The stability of thin film transistor inverters affects their further applications in the fields such as system on glass (SOG), etc. In this study, a simulation model of amorphous IGZO TFT devices was extracted based on the experimental data. In addition, the stretched-exponential equation between the threshold voltage change (ΔV_TH) and the bias stress time was obtained by fitting. Then, the variation of the electrical stability of traditional pseudo-CMOS inverters with bias stress time was explored, and an improved TFT inverter circuit was proposed, followed by the channel width adjustment and layout design. The revised inverter improves the high output voltage by 18.47% by delaying the pull-down transistor in the output stage. Meanwhile, the proposed inverter alleviates the effect of equivalent resistance increase caused by the threshold voltage shift on the output stage current through feedback, significantly improving its speed stability. When the bias stress time is 2.56×10⁷ s, the variation rate in its rise time is only 4.09%, far lower than the 296.11% of the traditional pseudo-CMOS inverters.