[4] [4] MCNUTT M J, LEMARQUIS S, DUNKLEY J L. Systematic capacitance matching errors and corrective layout procedures［J］. IEEE Journal of Solid-State Circuits, 1994，29（5）： 611-616.

[5] [5] ZHU Y, CHAN C H, CHIO U F, et al. A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS［J］. IEEE Journal of Solid-state circuits, 2010, 45（6）： 1111-1121.

[6] [6] ZHU Z, XIAO Y, WANG W, et al. A 1.33 W 10-bit 200KS/s SAR ADC with a tri-level based capacitor switching procedure［J］. Microelectronics Journal, 2013, 44（12）： 1132-1137.

[7] [7] LI H, SHEN Y, CANTATORE E, et al. Small-area SAR ADCs with a compact unit-length DAC layout［J］. IEEE Transactions on Circuits and Systems II： Express Briefs，2022, 69（10）： 4038-4042.

[8] [8] KONWAR S, ROY H, CHIANG S H W, et al. Deterministic Dithering-Based 12-b 8-MS/s SAR ADC in 0.18-m CMOS［J］. IEEE Solid-State Circuits Letters, 2022，5： 243-246.

[9] [9] LEE J H, LEE K Y. A Design of Low-Power Bootstrapped CMOS Switch for 20MS/s 12-bit Charge Sharing SAR ADCs［A］. Lee J H. 2021 18th International SoC Design Conference （ISOCC）［C］. Jeju： IEEE, 2021. 5-6.

[10] [10] VERMA D, SHEHZAD K, KIM S J, et al. Low power 10-BIT 8MS/s asynchronous SAR ADC with wake-up and sample logic for BLE application［A］. Verma D. 2020 International Conference on Electronics, Information, and Communication （ICEIC）［C］. Barcelona： IEEE, 2020.1-3.