The power consumption of successive approximation analog-to-digital converter （SAR ADC） is mainly derived from three modules： DAC, comparator and SAR logic. Among them, the energy consumed by DAC capacitor array during charge and discharge is an important factor affecting the overall power consumption of SAR ADC. Therefore, the design of low-power capacitor switch procedure is particularly critical. Traditional V_CM-based capacitor switch procedure is widely used in the design of SAR ADC capacitor switching schemes due to its relatively simple working principle and implementation mode. However, when the comparator results are opposite, the power consumption of switching will increase significantly. To solve this problem, this paper proposes a segmented capacitor split V_CM-based capacitor switch procedure, which can effectively reduce the power consumption of the capacitor switch, and designs a 12-bit 10MS/s low-power SAR ADC based on 65nm LP CMOS technology.