[1] [1] MENINGER S E, PERROTT M H. A 1-MHZ bandwidth 3.6-GHz 0.18-/spl mu/m CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise[J]. IEEE Journal of Solid-State Circuits, 2006, 41(4): 966-980.

[2] [2] YU X Y, SUN Y F, RHEE W, et al. An FIR-embedded noise filtering method for fractional-N PLL clock generators[J]. IEEE Journal of Solid-State Circuits, 2009, 44(9): 2426-2436.

[3] [3] PARK P, PARK D, CHO S. A 2.4 GHz fractional-N frequency synthesizer with high-OSR modulator and nested PLL[J]. IEEE Journal of Solid-State Circuits, 2012, 47(10): 2433-2443.

[4] [4] NANDWANA R K, ANAND T, SAXENA S, et al. A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method[J]. IEEE Journal of Solid-State Circuits, 2015, 50(4): 882-895.

[5] [5] KONG L, RAZAVI B. A 2.4-GHz 6.4-mW fractional-N inductorless RF synthesizer[J]. IEEE Journal of Solid-State Circuits, 2017, 52(8): 2117-2127.

[6] [6] WAN Z X, RHEE W, WANG Z H. Design and analysis of DTC-free bang-bang phase-locked loops[C]//IEEE International Symposium on Circuits and Systems. Daegu, Korea. 2021: 1-4.

[7] [7] DE MUER B, STEYAERT M S J. On the analysis of fractional-N frequency synthesizers for high-spectral purity[J]. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2003, 50(11): 784-793.

[8] [8] VERMA S, RATEGH H R, LEE T H. A unified model for injection-locked frequency dividers[J]. IEEE Journal of Solid-State Circuits, 2003, 38(6): 1015-1027.

[9] [9] RAZAVI B. A study of injection locking and pulling in oscillators[J]. IEEE Journal of Solid-State Circuits, 2004, 39(9): 1415-1424.

[10] [10] ADLER R. A study of locking phenomena in oscillators[J]. Proceedings of the IRE, 1946, 34(6): 351-357.

[11] [11] ZHANG Y T, XING Z, PENG Y, et al. A 2.9 GHz CMOS phase-locked loop with improved ring oscillator[C]//IEEE MTT-S International Wireless Symposium. Guangzhou, China. 2019: 1-3.

[12] [12] LIANG C F, WANG P Y. 10.8 A wideband fractional-N ring PLL using a near-ground pre-distorted switched-capacitor loop filter[C]//IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers. San Francisco, CA, USA. 2015: 1-3.