Fig. 1. Excess noise factor of APD FPA and GNDCD with different bias

Fig. 2. Comparison of this article and DRS in NEPh

Fig. 3. I-V curves of NMOS at 77 K and 300 K. The size of the NMOS is W/L=20 μm/0.55 μm

Fig. 4. ROIC overall block diagram

Fig. 5. TDC sequence chart

Fig. 6. The comparator schematic diagram

Fig. 7. Simulation results of input offset voltage of comparator

Fig. 8. Vernier TDC structural diagram

Fig. 9. The delay cell circuit

Fig. 10. Delay time for different temperatures and different bias voltages

Fig. 11. The schematic block diagram of TDC circuit Testing system

Fig. 12. Test sequence diagram

Fig. 13. Coarse counting test results at room temperature and low temperature

Fig. 14. Fine counting value at room temperature and low temperature test

Fig. 15. （a）Differential non-linearity，（b）integral non-linearity

Fig. 16. The output results of fine counting under different delay time