Fig. 1. (a) Schematic structure of the polarization-insensitive 4 × 4 MZI switch chip. The inset shows the on-chip polarization controller and the control system. (b) Microscope image of the fabricated silicon 4 × 4 optical switch chip. (c) Photo of the packaged chip.

Fig. 2. Normalized feedback port power P_f as a function of Δφ₁ and Δφ₂ with different combinations of input polarizations: (a) TE 25%, TM 75%; (b) TE 50%, TM 50%; (c) TE 75%, TM 25%; and (d) TE 100%.

Fig. 3. Flow chart of the polarization control algorithm.

Fig. 4. (a), (b) Polarization tuning process for two random polarization states. (c), (d) Recorded TIA voltages with randomly changed input polarization when the algorithm is (c) turned off and (d) turned on.

Fig. 5. Measured transmission spectra of the I₂−O₂ path for different input polarization states after polarization adjustment.

Fig. 6. Measured transmission spectra of one switching state at (a) port O₁, (b) port O₂, (c) port O₃, and (d) port O₄.

Fig. 7. Optical transmission measurement of a 32 Gbit/s OOK signal for various input polarization states: (a) eye diagrams and (b) BER as a function of received optical power.