Microelectronics, Volume. 54, Issue 1, 127(2024)

An Interconnect Capacitance Extraction Strategy of Integrated Circuit Based on Local Discontinuous Galerkin Method

ZHU Hongqiang1, SHAO Rumeng1, ZHAO Zhenghao1, YANG Hang2, TANG Jinpu2, and CAI Zhikuang2
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
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    References(11)

    [1] [1] SABELKA R, HARLANDER C, SELBERHERR S. The state of the art in interconnect simulation [C] // 2000 International Conference on Simulation of Semiconductor Processes and Devices. Seattle, WA, USA. 2000: 6-11.

    [2] [2] NAGARAJ N S, BONIFIELD T, SINGH A, et al. Benchmarks for interconnect parasitic resistance and capacitance [C] // International Symposium on Quality Electronic Design. San Jose, CA, USA. 2003: 163-168.

    [3] [3] DANG L R, SHIGYO N. Coupling capacitances for two-dimensional wires [J]. IEEE Electron Device Letters, 1981, 2(8): 196-197.

    [4] [4] SEIDL A, KLOSE H, SVOBODA M, et al. CAPCAL-a 3-D capacitance solver for support of CAD systems [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988, 7(5): 549-556.

    [5] [5] MCFEE S, WU Q, DORICA M, et al. Parallel and distributed processing for H-P adaptive finite-element analysis: a comparison of simulated and empirical studies [J]. IEEE Transactions on Magnetics, 2004, 40(2): 928- 933.

    [6] [6] CARSTEA I T, CARSTEA D P. Parallel computing in finite element applications [C] // Proceedings of the 10th WSEAS International Conference on Mathematical and Computational Methods in Science and Engineering. 2008: 180-185.

    [7] [7] ZHAI K, YU W. The 2-D boundary element techniques for capacitance extraction of nanometer VLSI interconnects [J]. International Journal of Numerical Modelling: Electronic Net-works, Devices and Fields, 2014, 27(4): 1-13.

    [8] [8] BATTERYWALA S H, DESAI M P. Variance reduction in Monte Carlo capacitance extraction [C] // Proceedings of 18th International Conference on VLSI Design Held Jointly with 4th International Conference on Embedded Systems Design. Kolkata, India. 2005: 85-90.

    [9] [9] YU W J, ZHUANG H, ZHANG C, et al. RWCap: a floating random walk solver for 3-D capacitance extraction of very-large-scale integration interconnects [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013, 32(3): 353-366.

    [10] [10] CASTILLO P, PERUGIA I, SHOTZAU D, et al. An a priori error analysis of the local discontinuous Galerkin method for elliptic problems [J]. SIAM Journal on Numerical Analysis, 2000, 38(5): 1676-1706.

    [11] [11] CASTILLO P. A review of the local discontinuous Galerkin (LDG) method applied to elliptic problems [J]. Applied Numerical Mathematics, 2006, 56(10-11): 1307-1313.

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    ZHU Hongqiang, SHAO Rumeng, ZHAO Zhenghao, YANG Hang, TANG Jinpu, CAI Zhikuang. An Interconnect Capacitance Extraction Strategy of Integrated Circuit Based on Local Discontinuous Galerkin Method[J]. Microelectronics, 2024, 54(1): 127

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    Paper Information

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    Received: Aug. 9, 2023

    Accepted: --

    Published Online: Aug. 7, 2024

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.230307

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